Digital PLL Calibration for PVT-Stable Phase Locking
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Solution Overview
Problem
Conventional digital phase-locked loops (PLLs) in integrated circuits (ICs) face stability issues due to variations in process-voltage-temperature (PVT) affecting the gains of the time-to-digital converter (TDC), digital loop filter, and divider circuit, leading to increased jitter and longer lock time.
Innovation Solution
A digital PLL comprising a TDC, digital loop filter, and divider circuit, where the loop transfer function is made independent of the TDC and divider circuit gains by using mesochronous sampling clock signals and enable signals generated based on calibration, allowing the digitally controlled oscillator (DCO) to generate clock signals based on filtered control data, thereby stabilizing the loop transfer function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog PLL components are used to generate clock signals, then frequency and phase control is achieved, but IC area occupation and manufacturing cost increase significantly
Solution Approach 1:
The patent replaces analog PLL components with digital logic circuits, substituting continuous analog signals with discrete digital signals. The phase detector, loop filter, and voltage-controlled oscillator are replaced with digital equivalents including XOR gate-based phase detector, digital filter logic, and digitally controlled oscillator using lookup tables and counters, thereby reducing IC area while maintaining clock generation accuracy
Solution Approach 2:
The patent changes the operating domain from analog to digital, transforming continuous parameters into discrete values. The analog voltage-controlled oscillator is replaced with a digital oscillator that uses integer-based frequency division and phase accumulation, allowing precise control through digital parameters while reducing hardware complexity and area
2Device complexity
If conventional digital PLL with PVT-sensitive components is used, then circuit complexity is reduced, but stability and jitter performance deteriorate due to PVT variations
Solution Approach 1:
The patent implements preliminary calibration of the digitally controlled oscillator during manufacturing to compensate for process variations. Calibration data is stored in lookup tables that are pre-computed to offset PVT effects, allowing the digital PLL to maintain stability without requiring complex real-time compensation circuits
Solution Approach 2:
The patent uses feedback from the phase detector to continuously adjust the digitally controlled oscillator. The phase difference detected between reference and feedback clocks is fed back through the digital loop filter to correct frequency and phase deviations, compensating for PVT variations dynamically while maintaining simple circuit architecture
3Manufacturing precision
If TDC and divider circuit gains are made sensitive to PVT variations, then manufacturing precision is simplified, but loop transfer function stability and jitter performance worsen
Solution Approach 1:
The patent uses integer-based frequency division ratios that are copied from pre-determined values stored in the digitally controlled oscillator. These integer ratios are insensitive to PVT variations because they rely on digital counting rather than analog timing, effectively copying precise frequency relationships without manufacturing sensitivity
Solution Approach 2:
The patent replaces the analog time-to-digital converter with a digital counter-based frequency divider. Instead of measuring time intervals with analog circuits that are sensitive to PVT, the system uses digital counters to divide frequencies by integer ratios, eliminating PVT sensitivity in the gain elements while maintaining loop stability
Data Source
AI summary
A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.