Multi-Mode Digital PLL Switching for Phase Noise Control
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Solution Overview
Problem
Current phase noise cancellation techniques in wireless communication systems, such as Wi-Fi and 5G, require sophisticated and energy-hungry components to meet stringent integrated phase noise requirements, leading to increased power dissipation and area usage, especially at higher modulation orders.
Innovation Solution
The implementation of a phase noise equalization architecture using all-digital phase lock loops (ADPLLs) with a time-to-digital converter (TDC) to estimate and cancel phase noise, allowing for the use of higher or lower phase noise PLLs based on modulation order demands, and an adaptive filter to match phase noise profiles, thereby reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sophisticated phase noise cancellation components are used, then phase noise performance is improved, but power dissipation increases
Solution Approach 1:
The patent changes the performance parameters of the PLL by dynamically adjusting the reference clock frequency and TDC resolution based on modulation order requirements. For higher modulation orders, the system uses a higher reference clock frequency and greater TDC resolution to achieve lower phase noise, while for lower modulation orders, it reduces these parameters to save power. This parameter adaptation resolves the contradiction by matching PLL performance to actual needs rather than maintaining constant high performance.
Solution Approach 2:
The patent implements dynamic switching between different PLL performance modes based on real-time modulation order detection. The system transitions between high-performance mode (with higher power consumption) and low-performance mode (with lower power consumption) according to the required modulation order. This dynamic adaptation allows the system to achieve good phase noise performance only when needed, resolving the power-performance contradiction.
2Reliability
If sophisticated phase noise cancellation components are used, then phase noise performance is improved, but area increases
Solution Approach 1:
The patent uses parameter changes to achieve high phase noise performance only when required by the modulation order. By adjusting the reference clock frequency and TDC resolution dynamically, the system avoids permanently implementing high-performance components that would occupy excessive area. The area is optimized by implementing multiple performance modes sharing the same physical resources rather than dedicating separate high-performance components for all operating conditions.
Solution Approach 2:
The patent makes the PLL components multi-functional by designing them to operate at different performance levels for different modulation orders. The same TDC, reference clock, and PLL circuitry serve both high-performance and low-performance requirements by adjusting their operating parameters. This universality eliminates the need for separate component sets for different performance levels, reducing overall area while maintaining the capability to achieve low phase noise when needed.
3Reliability
If higher reference clock frequency is used, then phase noise is reduced, but power consumption increases
Solution Approach 1:
The patent directly applies parameter changes by dynamically adjusting the reference clock frequency based on modulation order requirements. For high-order modulations (e.g., 256-QAM, 1024-QAM), the system uses a higher reference clock frequency (e.g., 19.2 MHz or 38.4 MHz) to achieve lower phase noise. For lower-order modulations, it switches to a lower reference clock frequency to reduce power consumption. This dynamic parameter adjustment resolves the contradiction between phase noise performance and power consumption.
4Reliability
If higher TDC resolution is used, then phase noise is reduced, but power consumption and area increase
Solution Approach 1:
The patent changes the TDC resolution parameter dynamically based on modulation order requirements. For higher modulation orders requiring lower phase noise, the system configures the TDC with higher resolution (more bits for phase difference measurement). For lower modulation orders, it reduces TDC resolution to decrease power consumption and area. This parameter adaptation resolves the contradiction by matching TDC performance to actual system needs.
Data Source
AI summary
Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.