Digital PLL Phase Switching for Lower Phase Noise
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Solution Overview
Problem
Existing digital phase-locked loops (PLLs) in frequency synthesizers face challenges in reducing phase noise, particularly when the time-to-digital converter (TDC) has nonlinear conversion characteristics, leading to increased spurious signals and phase noise in the generated clock signal.
Innovation Solution
A digital PLL configuration that includes a reference-phase generation circuit, an oscillating circuit, a signal generation circuit, and a phase detection circuit, where the signal generation circuit generates multiple phase-varying second clocks and switches them multiple times within each cycle period, allowing the phase detection circuit to accurately determine the phase value and reduce phase noise even with nonlinear TDC characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a digital PLL is used to reduce layout area and power consumption, then device area and power consumption are reduced, but phase noise reduction becomes more difficult
Solution Approach 1:
The signal generation circuit segments the clock signal generation into multiple phase-varying second clocks (e.g., four clocks with 90-degree phase differences). By dividing the single clock signal into multiple phase-separated signals and switching between them, the system achieves better phase noise characteristics while maintaining digital PLL advantages of reduced area and power consumption.
Solution Approach 2:
The signal generation circuit implements periodic switching of the plurality of second clocks within each cycle period of the reference clock. This periodic action creates a third clock with reduced phase noise by systematically varying the phase of output clocks in a controlled periodic manner, addressing the phase noise challenge in digital PLLs.
2Device complexity
If the TDC has nonlinear conversion characteristics, then device complexity is reduced, but spurious signals and phase noise increase
Solution Approach 1:
The invention converts the harmful effect of nonlinear TDC characteristics into a beneficial outcome. By using multiple phase-varying second clocks and switching between them periodically, the system compensates for TDC nonlinearity-induced spurious signals. The phase variation and switching mechanism distributes and reduces the impact of nonlinear conversion errors, transforming what would be harmful spurious signals into acceptable phase noise levels.
Solution Approach 2:
The signal generation circuit changes the phase parameter of the clock signals by generating multiple second clocks with different phase relationships (e.g., 0°, 90°, 180°, 270°). This parameter variation allows the system to overcome TDC nonlinearity effects by selecting and switching between different phase states, thereby reducing spurious signals while maintaining simple TDC design.
3Measurement precision
If multiple phase-varying clocks are generated and switched, then phase noise is reduced, but device complexity increases
Solution Approach 1:
The signal generation circuit merges the functions of multiple clock generators into a single integrated circuit that produces a plurality of phase-varying second clocks from one first clock. By combining multiple clock generation functions and the switching mechanism into one unified block, the system achieves phase noise reduction without proportionally increasing overall device complexity.
Data Source
AI summary
A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.