Digital PLL Architecture Using PLDDS for Portable Clock Synthesis
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Solution Overview
Problem
The portability of digital PLL designs is limited due to the need for mixed signal simulation, which increases design verification time and effort, and the scaling down of semiconductor fabrication processes leads to increased design rule constraints, resulting in higher design costs.
Innovation Solution
A phase-locked direct digital synthesizer (PLDDS) is used, incorporating a free-running oscillator, phase-locked direct digital synthesizer, phase interpolator, sampling D flip-flop, digital loop filter, rotational accumulator, retimer, and coarse frequency lock to generate a clock signal with reduced out-of-band noise and improved frequency synthesizer portability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If digital PLL is used instead of analog PLL, then chip area and power consumption are reduced, but design verification complexity increases due to mixed signal simulation requirements
Solution Approach 1:
The patent replaces the traditional mixed-signal verification approach with a pure software simulation method. By implementing the PLL as a synthesizable circuit that can be fully verified through behavioral simulation and timing analysis without requiring mixed-signal simulation, it substitutes complex verification machinery with simpler verification tools, thereby reducing design verification complexity while maintaining the digital implementation benefits.
2Manufacturing precision
If semiconductor fabrication process is scaled down, then integration density and performance are improved, but design rule constraints increase leading to higher design costs
Solution Approach 1:
The patent employs extensive use of synthesis directives and configurable parameters that allow the circuit to be automatically adapted to different fabrication process nodes. By using synthesis tools that can optimize the design for specific process rules and by implementing the PLL with parameters that can be adjusted without redesign, the patent reduces the impact of increased design rule constraints, thereby lowering design costs despite process scaling.
3Adaptability or versatility
If analog PLL is used, then frequency synthesis is achieved, but sensitivity to PVT variation and high power consumption occur
Solution Approach 1:
The patent completely replaces the analog PLL architecture with a digital PLL implementation. The frequency synthesis function is achieved through digital counters, dividers, and phase detectors implemented in standard digital CMOS logic. This substitution eliminates the need for analog components that consume high power and are sensitive to PVT variations, while maintaining full frequency synthesis capability through digital frequency division and phase comparison.
Data Source
AI summary
The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system.The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range.Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.