Digital PLL Output Alignment Using Advanced Pulse Groups
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Solution Overview
Problem
Existing digital phase-locked loops (DPLLs) face challenges in aligning output clocks with reference clocks at low frequencies due to hardware delays, requiring lengthy averaging processes that compromise alignment accuracy and efficiency, especially when multiple outputs share a common feedback channel.
Innovation Solution
A method that advances output pulses during alignment to reduce spacing, determines delay values over a group of pulses, and compensates for hardware delays by adjusting pulse timing, allowing for faster alignment without sacrificing precision, utilizing a software-controlled oscillator and feedback circuit to drive hardware oscillators and pattern shifters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If averaging is performed over many clock samples to improve alignment accuracy, then measurement precision is improved, but alignment time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between output frequency and required phase shift values before actual alignment is needed. When alignment is required, the system simply looks up the pre-computed values corresponding to the current output frequency, avoiding the need to perform time-consuming averaging measurements at that moment. This resolves the contradiction by preparing accuracy data in advance, making high-precision alignment available instantly without requiring long measurement periods.
Solution Approach 2:
The system cushions against the time penalty of averaging by pre-computing alignment parameters for all possible output frequencies and storing them in a lookup table. This beforehand preparation ensures that when alignment is needed at any frequency, the system already has the correct phase shift values ready, eliminating the need to wait for lengthy averaging processes during actual operation.
2Device complexity
If multiple outputs share a common feedback channel, then device complexity is reduced, but alignment time increases due to sequential processing requirements
Solution Approach 1:
The patent resolves the sequential processing bottleneck by performing preliminary computation of alignment parameters for all possible frequencies before multiple outputs need alignment. The lookup table is pre-populated with phase shift values for all frequency ranges, allowing multiple outputs to quickly retrieve their alignment parameters without waiting for sequential averaging measurements. This maintains the simple shared feedback channel structure while eliminating the time penalty of sequential processing.
3Speed
If output frequency is reduced to meet low frequency requirements, then application requirements are satisfied, but alignment measurement time increases proportionally
Solution Approach 1:
The patent decouples output frequency from measurement time by pre-computing alignment parameters for all possible output frequencies including low frequencies. The lookup table stores phase shift values corresponding to each frequency, allowing the system to generate low frequency outputs (e.g., 1 Hz) without requiring proportionally long measurement times. The alignment parameters for low frequencies are calculated and stored in advance, enabling instant retrieval regardless of the actual output frequency being used.
Data Source
AI summary
To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.