Digital PLL Delay-Line Switching to Eliminate PVT Glitches
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Solution Overview
Problem
Existing digital phase locking loops (DPLLs) experience glitches during dynamic compensation of Process, Voltage, and Temperature (PVT) influences, leading to abnormal operation of sensitive circuits and systems.
Innovation Solution
A digital phase locking loop with a trigger and a delay line, where the trigger samples a selection signal of a first delay element using a delayed clock signal and outputs it to a second delay element, ensuring that selection end transitions occur after the rising edge of the clock input signal, thereby avoiding glitches during delay updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of delay elements is dynamically adjusted to compensate for PVT influences, then the delay compensation accuracy is improved, but glitches occur during the transition of selection ends
Solution Approach 1:
The trigger samples the selection end signal of the first delay element before the transition occurs, using the delayed clock signal as the sampling clock. This preliminary sampling captures the selection state at the appropriate moment, preventing glitches during the transition to the second delay element.
Solution Approach 2:
The trigger uses the delayed clock signal (which is the output of the delay line) as the sampling clock to sample the selection end signal. This feedback mechanism ensures that the sampling occurs at the correct phase relative to the clock input signal, synchronizing the transition with the clock edge and eliminating glitches.
2Speed
If selection end transitions occur at any time to update delay elements, then the response speed to PVT changes is improved, but glitches are generated that cause abnormal operation of sensitive circuits
Solution Approach 1:
The trigger samples the selection end signal periodically using the delayed clock signal as the sampling clock. This ensures that transitions to the second delay element occur only at specific phases of the clock cycle (synchronized with the clock edge), preventing random-time transitions that would cause glitches in sensitive circuits.
Solution Approach 2:
The trigger acts as an intermediary between the first and second delay elements. It samples the selection end signal of the first delay element and uses this sampled signal to control the selection end of the second delay element, ensuring that transitions are synchronized with the clock edge and do not cause glitches.
3Measurement precision
If multiple delay elements are used to achieve precise delay control, then the delay adjustment range is improved, but the complexity of the delay line structure increases
Solution Approach 1:
The delay line is segmented into multiple delay elements (first delay element, second delay element) that can be selectively activated. The trigger controls the selection ends of these segmented delay elements, allowing precise delay control by adjusting which segments are active while keeping the overall structure manageable through systematic control.
Data Source
AI summary
The present disclosure discloses a digital phase locking loop and a method. The digital phase locking loop includes a trigger and a delay line. The trigger receives a delayed clock signal output by the delay line, and receives a signal of a selection end of a first delay element in the delay line; the selection end is in a gating state before triggering of the trigger. The trigger samples the signal of the selection end of the first delay element, and outputs the sampled signal to a selection end of a second delay element in the delay line; the selection end of the second delay element is in the gating state after triggering of the trigger. The signal of the selection end of the first delay element is sampled by the trigger, and the sampled result is used as the signal of the selection end of the second delay element, thus reducing glitches caused by transition.