Digital PLL With PWM Proportional Path for Low Jitter
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Solution Overview
Problem
Digital phase locked loops (PLLs) face challenges with high quantization noise and jitter due to large loop gain factors required for stability and high bandwidth, and time-to-digital converters (TDCs) are expensive and complex to implement, limiting their performance.
Innovation Solution
A digital PLL with an analog proportional control function using a phase frequency detector (PFD) that outputs pulse width modulated signals, directly connected to a digitally controlled oscillator (CO), allowing for low power, low jitter, and low area architecture with reduced quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large loop gain factors are used in digital PLL to guarantee loop stability and achieve high bandwidths, then loop stability and bandwidth are improved, but quantization noise and jitter performance deteriorate
Solution Approach 1:
The invention segments the control function into two independent paths: a digital integral path for long-term stability and an analog proportional path for immediate response. This segmentation allows each path to operate optimally without the trade-offs of using a single high-gain digital path, thereby reducing quantization noise while maintaining bandwidth.
Solution Approach 2:
The invention merges digital and analog control techniques by combining a digital integral path with an analog proportional path. This hybrid approach leverages the advantages of both digital (precision, stability) and analog (continuous control, low noise) domains to achieve high bandwidth with low quantization noise.
2Measurement precision
If TDC is used as the phase detector in digital PLL to improve performance, then phase detection accuracy is improved, but power consumption, area, and complexity increase significantly
Solution Approach 1:
The invention extracts only the essential function of phase detection from the complex TDC architecture by using a simple PFD that generates pulse width modulated signals. This extracted function is then processed by the dual-path control circuit, achieving high performance without the complexity, power, and area overhead of a full TDC.
Solution Approach 2:
The invention creates a functional copy of the TDC's phase detection capability using a PFD with pulse width modulation. This copy achieves the necessary measurement precision through the combination of PFD output and the dual-path control mechanism, avoiding the need for expensive TDC hardware.
3Object-generated harmful factors
If analog PLL is used to achieve low jitter and high bandwidth performance, then jitter and bandwidth performance are improved, but circuit area and power requirements increase
Solution Approach 1:
The invention substitutes the mechanical/analog control system with a hybrid digital-analog system. The analog proportional path provides continuous control similar to traditional analog PLLs, while the digital integral path and PFD replace bulky analog components, achieving low jitter with reduced circuit area.
Data Source
AI summary
Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.