Digital PLL with PWM Phase Control for Low Jitter Locking
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Solution Overview
Problem
Digital phase locked loops (PLLs) face challenges with high quantization noise and jitter due to large loop gain factors required for stability and high bandwidth, and time-to-digital converters (TDCs) are expensive and complex to implement, limiting their performance.
Innovation Solution
A digital PLL with an analog proportional control function using a phase frequency detector (PFD) that outputs pulse width modulated signals, directly connected to a digitally controlled oscillator (CO), allowing for low power, low jitter, and low area architecture with reduced quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large loop gain factors are used in digital PLL to guarantee loop stability and achieve high bandwidths, then loop stability and bandwidth are improved, but quantization noise and jitter performance deteriorate
Solution Approach 1:
The patent changes the parameter of loop gain from large to small by implementing a novel digital PLL architecture with a modified phase detector that outputs three states (UP, HOLD, DOWN) instead of traditional two states. This parameter change allows the system to achieve high bandwidth with small loop gain factors, thereby reducing quantization noise while maintaining loop stability.
Solution Approach 2:
The patent segments the control signal generation into three distinct states (UP, HOLD, DOWN) rather than using traditional binary control. This segmentation allows for finer control granularity, enabling the system to achieve high bandwidth without requiring large loop gain factors that would otherwise be necessary, thus reducing quantization noise.
2Measurement precision
If TDC is used as the phase detector in digital PLL to improve performance, then phase detection accuracy is improved, but power consumption, area, and complexity increase
Solution Approach 1:
The patent replaces the expensive and complex TDC (time-to-digital converter) with a simpler, lower-cost phase detector implementation that achieves comparable performance. The new phase detector uses basic digital logic circuits instead of complex TDC architecture, significantly reducing implementation complexity while maintaining sufficient phase detection accuracy for the application.
Solution Approach 2:
The patent creates a simplified copy of the phase detection function that achieves the essential performance without replicating the full complexity of TDC. By implementing a three-state phase detector using standard digital logic, the system captures the core functionality needed for accurate phase detection while avoiding the overhead of a complete TDC implementation.
3Use of energy by moving object
If traditional digital PLL architecture is used to reduce power and area compared to analog PLL, then power consumption and circuit area are reduced, but jitter performance deteriorates
Solution Approach 1:
The patent changes the control signal parameter from binary (two states) to ternary (three states), enabling the digital PLL to achieve jitter performance comparable to analog PLLs. This parameter change allows for smoother frequency adjustments and reduces quantization effects, thereby reducing jitter while maintaining the power and area advantages of digital implementation.
Solution Approach 2:
The patent introduces dynamic behavior through the three-state control mechanism that can adaptively switch between UP, HOLD, and DOWN states based on real-time phase error conditions. This dynamic control allows the system to optimize performance by holding the frequency steady when phase error is minimal, thereby reducing jitter, while maintaining the energy efficiency of digital logic.
Data Source
AI summary
Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.