Digital PLL Reference Delay for Low-Noise Fractional-N Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital phase locked loops (DPLLs) face issues with high power consumption in the time to digital converter (TDC) delay line, significant current consumption during sampling, offset between the TDC and synchronization circuit, and frequency spurs, which affect their performance.
Innovation Solution
A digital phase locked loop with an adjustable delay component, such as a digital to time converter (DTC), that applies a time delay to the reference clock signal to improve quantization error and reduce phase noise and non-linearities by enabling more accurate phase representation of the digitally controlled oscillator (DCO), allowing for bang-bang operation while maintaining fractional-N mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a time to digital converter (TDC) delay line is used to measure phase, then phase measurement capability is provided, but power consumption increases due to the delay line running at output clock frequency
Solution Approach 1:
The patent replaces the traditional TDC delay line (analog/time-domain mechanism) with a digital counter-based timing component. The delayed reference clock signal is generated digitally through counting cycles, substituting the continuous analog delay mechanism with a discrete digital counting approach, thereby reducing power consumption while maintaining phase measurement capability
Solution Approach 2:
The patent employs periodic sampling of the phase difference using a timing component that counts reference clock cycles. Instead of continuously operating a high-power delay line, the system periodically measures phase by counting cycles between edges, enabling power-efficient phase measurement through time-discretized periodic action
2Measurement precision
If a timing component samples the phase signal, then phase information is obtained, but current consumption increases during the sampling period
Solution Approach 1:
The timing component operates periodically rather than continuously, sampling phase information only at necessary intervals. The component counts reference clock cycles between specific events and then resets, creating periodic operation cycles that reduce average current consumption compared to continuous sampling operations
Solution Approach 2:
The timing component uses the existing reference clock signal itself as the counting clock, eliminating the need for separate high-frequency sampling clocks. The reference clock serves dual purposes: as the signal being measured and as the timing reference for measurement, reducing additional power requirements
3Measurement precision
If an adjustable delay component is added to improve quantization error, then phase measurement accuracy improves, but device complexity increases
Solution Approach 1:
The patent introduces an adjustable delay component that dynamically modifies the reference clock signal delay based on feedback from the phase measurement. This dynamic adjustment allows the system to optimize quantization error compensation adaptively, improving measurement accuracy without requiring a completely complex fixed architecture
Solution Approach 2:
The adjustable delay component is controlled by feedback from the phase measurement process. The system measures phase difference, calculates required delay adjustment, and applies compensatory delay to the reference clock signal, creating a feedback loop that improves quantization accuracy while using simple controllable delay elements
Data Source
Figure 1~2
Figure 3~4
Figure 5a)~5b)
AI summary
A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318). The digital phase locked loop further comprising a timing component (320) configured to process the delayed reference clock signal (318) and the output clock signal (304), and generate a first control signal (322) representative of the phase of the output clock signal (304); a reference accumulator (310) configured to receive the channel command word (308) and generate: a second control signal (312) representative of the phase of an intended output clock signal; and the time delay control signal (316) such that the delayed reference clock signal (318) is delayed by a period of time representative of a first portion of the phase of the intended output clock signal. The digital phase locked loop also comprising a controller (314) configured to process the first and second control signals (322, 312), and generate a DCO control signal (326) for setting the frequency of a digitally controlled oscillator (328) in accordance with the first and second control signals (322, 312); and a digitally controlled oscillator (328) configured to generate the output clock signal (304) in accordance with the DCO control signal (326).