Software-Reconfigurable Digital PLL for Multi-Standard RF Spur Reduction
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Solution Overview
Problem
Conventional all digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unacceptable RF spurs.
Innovation Solution
A software-based ADPLL architecture with a reconfigurable calculation unit (RCU) that can perform all atomic operations within a single reference clock cycle, using an application-specific instruction-set processor (ASIP) to optimize PLL calculations and reduce silicon area and RF spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardwired ADPLL design is used, then the circuit operates at lower speed with dedicated hardware, but it lacks reconfigurability and cannot support multi-standard wireless applications
Solution Approach 1:
The patent implements a universal processor core that can execute different instruction sets to perform various ADPLL functions. The processor includes a reconfigurable instruction set that can be programmed to support multiple wireless standards (GSM, WCDMA, Bluetooth, WiFi, WiMAX) through software configuration rather than hardware changes, enabling one circuit to perform multiple functions.
Solution Approach 2:
The patent replaces the traditional mechanical/hardwired ADPLL circuit with a software-based processor system. Instead of fixed hardware logic gates and circuits, the invention uses a programmable processor with instruction memory that can be reconfigured through software to implement different PLL algorithms and functions, substituting physical reconfiguration with digital/software reconfiguration.
2Adaptability or versatility
If a hardwired ADPLL design is used, then the circuit structure is fixed, but any modification requires numerous time-consuming steps in the ASIC creation process
Solution Approach 1:
The patent creates a dynamic system where the ADPLL functionality can be changed at runtime through software updates rather than requiring physical redesign. The processor can load different instruction sets and configuration parameters to adapt to new standards or requirements, making the system flexible and updatable without going through the lengthy ASIC re-spin process.
Solution Approach 2:
The patent enables modification of ADPLL behavior by changing software parameters and instruction sets rather than hardware parameters. Configuration variables, filter coefficients, and control algorithms can be adjusted through software to optimize performance for different standards, eliminating the need for physical design changes and associated time losses.
3Object-affected harmful factors
If conventional ADPLL circuits are used, then the hardware implementation is simple, but they generate significant current transients that result in unacceptable RF spurs
Solution Approach 1:
The patent replaces the traditional analog/hardwired PLL circuit with a fully digital processor-based system. This substitution allows for precise control of current switching timing and distribution, enabling the system to minimize current transients through software-controlled sequencing and spreading techniques, thereby reducing RF spur generation.
Solution Approach 2:
The patent introduces a processor as an intermediary between the reference clock and the VCO control. This intermediary can process and distribute control signals in a controlled manner, spreading current consumption over time and reducing peak transients that would otherwise directly modulate the VCO and create RF spurs.
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.