Digital PLL Circuit for Single-Phase AC Noise Immunity
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Solution Overview
Problem
Existing AC devices face challenges in synchronizing with single-phase electrical systems, particularly due to noise vulnerabilities at zero crossing points, which affect phase and frequency locking.
Innovation Solution
A Phase Locked Loop (PLL) circuit is implemented, utilizing a digital signal processor to generate a product signal, calculate phase and frequency correction signals, and adjust the clock rate to lock with the input signal, enhancing synchronization robustness across various AC devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If zero crossing detection is used for phase and frequency locking in single-phase electrical systems, then the approach is straightforward and simple to implement, but it suffers from vulnerability to noise occurring at or around the zero crossing points
Solution Approach 1:
The patent introduces an intermediary signal processing approach between the raw zero-crossing detection and the phase-locked loop. Instead of directly detecting zero crossings, the system uses a reference waveform generator that produces a clean reference signal, which is then compared with the input signal. This intermediary reference waveform acts as a mediator that eliminates the direct exposure to noise at zero crossing points while maintaining the simplicity of the approach.
Solution Approach 2:
The patent replaces the mechanical/analog zero-crossing detection method with a digital signal processing approach. By using digital waveform generation and comparison, the system achieves noise immunity without sacrificing simplicity. The digital implementation allows for precise control and filtering of the reference waveform, eliminating the vulnerability to noise that plagues analog zero-crossing detectors.
2Reliability
If three-phase synchronization approaches are used, then phase and frequency locking can be achieved in three-phase systems, but the approach is not amenable to single-phase electrical systems
Solution Approach 1:
The patent creates a universal phase-locked loop design that can function in both single-phase and three-phase systems. The core methodology uses a reference waveform generator that can be configured for different phase systems. By making the reference waveform generation adaptable, the same basic architecture serves multiple functions - it works for single-phase systems where simplicity is needed, and can be extended to three-phase systems where higher accuracy is required, thus achieving universality.
Solution Approach 2:
The patent introduces dynamic adaptability to the phase-locked loop system. The reference waveform generator can dynamically adjust its parameters based on the input signal characteristics. This dynamic behavior allows the system to optimize its performance for the specific application - whether single-phase or three-phase - making the approach versatile across different electrical system configurations while maintaining reliable phase locking.
Data Source
AI summary
A phase locked loop (PLL) circuit provides ac devices, such as power inverters and power measurement devices, with a reliable means for synchronizing to ac electrical systems. In an exemplary embodiment, the PLL circuit is configured for operation with single-phase electrical systems and offers substantial noise immunity by basing its locking operations on measured fundamental components, i.e., measured x-y phasors, of the electrical system voltage. Further, with its phasor-based locking operations and with its timer/counter-based operation, the PLL circuit can be implemented partly or wholly in digital processing logic.