Digital Phase-Locked Loop Integer Channel Spur Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current cellular phone handsets face challenges in reducing size and cost due to the immaturity of advanced processes for analog/RF designs, with 30-40% of board space occupied by analog/RF functionality that cannot be easily migrated to newer technology nodes, hindering the addition of features and footprint reduction.
Innovation Solution
The development of an interpolative all-digital phase locked loop (iADPLL) that operates on clock signals derived from an RF clock signal, featuring a controllable oscillator, phase detection circuit, and resamplers, which reduces reference spurs, improves spectral and phase-domain performance, and incorporates a Hybrid Stochastic Gradient KDCO inverse calibration algorithm for accurate gain estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog/RF circuitry is used to maintain performance, then reliability is improved, but area of stationary object increases and ease of manufacture deteriorates
Solution Approach 1:
The patent replaces analog/RF circuitry with digital circuitry implementation. Specifically, the phase-locked loop and frequency synthesizer functions traditionally implemented in analog domain are migrated to digital domain using digital signal processing techniques, thereby reducing the board space occupied by analog/RF functionality while maintaining the required RF performance through mathematical modeling and digital control algorithms
Solution Approach 2:
The patent changes the fundamental operating parameters from analog continuous signals to digital discrete signals. By representing RF signals and control parameters in digital form, the system achieves better integration density and scalability, allowing multiple RF functions to be consolidated on a smaller footprint while maintaining performance through precise digital parameter control
2Reliability
If analog/RF circuitry is used to maintain performance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent substitutes complex analog/RF circuit designs with digital circuit implementations. The phase-locked loop, frequency synthesizer, and modulation/demodulation functions are realized through digital logic and signal processing algorithms, which are inherently more modular and easier to design, simulate, and modify compared to traditional analog approaches
Solution Approach 2:
The patent creates a universal digital platform that can perform multiple RF functions. The same digital infrastructure supports frequency synthesis, modulation, demodulation, and signal processing across different RF standards and bands, reducing overall system complexity by eliminating the need for separate analog circuitry for each function
3Area of stationary object
If digital circuitry is used to reduce area, then area of stationary object decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces analog/RF circuitry with digital circuitry that can be manufactured using standard CMOS digital process nodes. By implementing RF functions in the digital domain, the system leverages the mature and precise digital fabrication processes that operate at larger feature sizes compared to advanced analog/RF processes, thereby reducing manufacturing precision requirements while achieving compact integration
Data Source
AI summary
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.