Digital PLL PID Loop Filter With Feedback Spur Suppression
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Solution Overview
Problem
Conventional digital phase-locked loop (PLL) circuits face challenges such as limited frequency division by integer values, quantization noise, and high frequency spurs that increase jitter, making it difficult to accurately synthesize frequency signals with reduced or eliminated frequency spurs in compact digital PLL circuits.
Innovation Solution
A modified proportional-integral-derivative (PID) loop filter is implemented with a differential high pass filter feedback element and a transformed feedback module, including programmable gain elements to mimic low pass filters, which reduces jitter and frequency variation by suppressing high frequency noise in the digitally controlled oscillator (DCO) output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional PID controller is used in a digital PLL circuit, then the circuit can be implemented with discrete components, but high frequency spurs appear at the DCO output increasing jitter
Solution Approach 1:
The patent implements a feedback path that feeds a portion of the DCO output signal back to the input of the PID controller. This feedback mechanism allows the system to detect and correct high frequency spurs and quantization noise by continuously adjusting the control signal based on the actual DCO output, thereby reducing jitter while maintaining discrete component implementation
Solution Approach 2:
Instead of trying to prevent high frequency spurs at the source, the patent inverts the approach by feeding the DCO output back to the PID input, allowing the system to react to and correct the spurs after they occur. This inversion enables the discrete PID implementation to actively suppress jitter through feedback correction
2Device complexity
If digital PLL circuits use integer division only, then the circuit design is simplified, but frequency synthesis precision is limited
Solution Approach 1:
The patent makes the division ratio dynamic by allowing it to be adjusted based on the feedback signal from the DCO output. The division ratio is no longer fixed at an integer value but can be dynamically modified to achieve precise frequency synthesis while maintaining relatively simple circuit design through the use of the existing PID controller structure
3Measurement precision
If the PID controller gain is increased to reduce quantization noise, then frequency synthesis accuracy improves, but high frequency spurs and jitter increase
Solution Approach 1:
The feedback path allows the system to use higher PID gains for better frequency synthesis accuracy while the feedback mechanism simultaneously suppresses the resulting high frequency spurs and jitter. The feedback continuously adjusts the control signal to counteract the adverse effects of high gain, enabling both improved accuracy and reduced spurs
Data Source
AI summary
A PID loop filter control method and apparatus are provided for generating a control signal to control a digitally controlled oscillator which generates a phase locked loop clock signal, where the PID loop filter includes a proportional-integral-derivative (PID) controller connected and configured to produce a PID controller output signal, and a transformed feedback module having a feedback summer circuit and internal gain stage connected in series to produce an M-bit control signal in response to the PID controller output signal, wherein an output from internal gain stage is provided over a feedback path comprising a feedback gain stage having a configurable Kfb gain value (e.g., 0<Kfb<4) and a filter element to produce the internal feedback signal which is summed with the PID controller output signal to low pass filter high frequency spurs and noise from the PID controller output signal.