Digital PLL Clock Selection to Reduce Multi-Band Spurious Interference
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Solution Overview
Problem
In wireless communication systems, particularly in mobile phones, digital type PLL circuits generate spurious signals that can interfere with communication quality, especially when multiple frequency bands are used, leading to noise in the receiving signal due to overlapping spurious frequencies and transmission modulation signals.
Innovation Solution
A high-frequency signal processing device is designed with a digital phase comparator unit, digital filter unit, digital control oscillator unit, and frequency divider unit, which selects an appropriate clock frequency for the digital filter unit based on the frequency band to minimize the influence of spurious signals by setting the DLPF clock frequency to avoid overlap with desired frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a digital type PLL circuit is used in the high-frequency signal processing unit, then the device area is reduced and power consumption is lowered, but spurious signals are generated that interfere with communication quality
Solution Approach 1:
The patent changes the clock frequency parameter of the digital filter unit to resolve spurious signal interference. By selecting a clock frequency that is not an integer divisor of the spurious frequency, the spurious components are distributed across multiple frequency bins, preventing concentration at a single interfering frequency. This parameter adjustment maintains the benefits of digital PLL while eliminating the harmful spurious effects.
2Speed
If the clock frequency of the digital filter unit is increased to improve processing speed, then higher performance is achieved, but spurious signals at higher frequencies may overlap with desired signal bands
Solution Approach 1:
The patent implements dynamic clock frequency selection based on the operating frequency band. The system automatically adjusts the digital filter unit's clock frequency according to the current transmission band, choosing frequencies that avoid spurious overlap with desired signal bands. This dynamic adaptation allows the system to maintain optimal processing speed while preventing spurious interference in each specific operating condition.
3Reliability
If additional filters like SAW filters are added to eliminate spurious signals, then communication quality is improved, but device area increases and cost rises
Solution Approach 1:
The patent replaces physical filtering mechanisms (SAW filters, additional hardware) with a digital signal processing solution. By using the digital filter unit with carefully selected clock frequencies, spurious signals are suppressed through digital processing rather than physical filtration. This substitution eliminates the need for additional analog filters, reducing device area and cost while maintaining communication quality.
Data Source
AI summary
To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.