Digital PLL Startup Control to Suppress Frequency Overshoot
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Solution Overview
Problem
Digital PLL circuitry experiences overshoot in oscillation frequency during startup, leading to increased design constraints, longer lock-up time, and higher man-hours in circuit design due to the need for excessive STA constraint margins and PVT variations.
Innovation Solution
A digital PLL circuitry configuration that fixes the control code for the digitally controlled oscillator at startup to suppress oscillation frequency overshoot, using a sequence of first and second control codes to gradually adjust the oscillation frequency, reducing overshoot and lock-up time, and incorporating a frequency limiting signal to manage startup and normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the digitally controlled oscillator is used at startup, then the PLL circuitry can be fully digital, but oscillation frequency overshoot occurs
Solution Approach 1:
The startup control circuitry pre-sets a specific control code for the digitally controlled oscillator that limits the maximum oscillation frequency to a predetermined value during startup. This preliminary action prevents frequency overshoot before it occurs, allowing the PLL to transition from a fully digital architecture without suffering from the typical overshoot problems of conventional digital PLLs
2Reliability
If the maximum frequency is designed based on PVT conditions, then reliability is improved, but excessive STA constraint margin is required
Solution Approach 1:
The invention changes the control code parameter during startup to limit the oscillation frequency to a predetermined value that is lower than the maximum frequency. By dynamically adjusting the control code based on startup conditions rather than using the maximum frequency, the system achieves reliable operation under PVT variations while reducing the required STA constraint margin
3Speed
If the overshoot amount of oscillation frequency becomes large, then the digital PLL can operate at high frequency, but lock-up time increases
Solution Approach 1:
The startup control circuitry performs a preliminary action by presetting a control code that limits the oscillation frequency during startup. This prevents large frequency overshoot from occurring in the first place, allowing the PLL to reach the target frequency more quickly and reduce lock-up time while still achieving high-frequency operation once locked
Data Source
AI summary
A digital PLL circuitry, according to the present embodiment, includes: a phase difference arithmetic circuitry configured to arithmetically operate and output a phase difference between an input clock signal and an output clock signal; a first control code generation circuitry configured to generate a first control code for controlling an oscillation frequency based on the phase difference and a frequency control input being a control target frequency relating to the output clock signal, and output the first control code; a second control code generation circuitry configured to generate and output a second control code for controlling the oscillation frequency according to a sequence; a selection circuitry configured to select and output one of the first control code and the second control code as a selection control code; and a digitally controlled oscillator configured to output the output clock signal of the oscillation frequency according to the selection control code.