Digital PLL Phase Correction for Non-Integer Sync Pauses

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Solution Overview

Problem

Conventional phase locked loops experience a long transient regulation process due to a non-integer multiple pause length in the reference signal, leading to a significant phase difference and frequency variation when synchronizing a clock signal with a reference signal in digital transmission systems.

Innovation Solution

A method that generates a phase difference signal proportional to the phase difference between the clock and reference signals, filters it, and uses a digital oscillator to correct the phase of the clock signal by a fraction of the clock period at the end of the pause, maintaining the frequency and phase state during the pause, utilizing a phase correction value stored in an accumulator register.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the pause length is a non-integer multiple of the clock period, then the reference signal can accommodate variable pause durations, but a large phase difference occurs at the beginning of the second synchronization part resulting in a long transient regulation process

Engineering Contradiction:

Improvepause length flexibilityVSAvoidtransient regulation process duration

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent stores the fractional clock period value during the pause interval before the second synchronization part begins. This preliminary storage of correction data allows the system to quickly compensate for the phase difference when the pause ends, rather than gradually adjusting during a long transient process. The accumulator register holds the pre-calculated phase correction value ready for immediate application.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the operational parameters of the phase-locked loop by switching between different regulation modes. During the pause, the loop is effectively held in a steady state with stored parameters. When the second synchronization part begins, the stored fractional clock period parameter is applied to immediately correct the phase difference, transitioning the system from a potential long transient state to a synchronized state much faster than conventional continuous regulation would achieve.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If continuous regulation is maintained through the pause, then phase synchronization is maintained, but the clock signal frequency must change during the pause causing instability

Engineering Contradiction:

Improvephase synchronization continuityVSAvoidclock signal frequency stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies periodic regulation action rather than continuous regulation. The phase-locked loop performs regulation during the first synchronization part, then enters a hold state during the pause where the clock signal maintains its frequency and phase. A correction is applied at the beginning of the second synchronization part based on pre-stored fractional period values. This periodic approach (regulate-hold-correct) maintains reliability while ensuring frequency stability during the pause interval.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent prepares for the pause interval by storing the fractional clock period value in advance during the first synchronization part. This pre-calculated correction value acts as a cushion that prevents phase drift during the pause without requiring continuous frequency adjustments. The stored value compensates for the non-integer multiple pause length, cushioning against potential synchronization errors while maintaining frequency stability.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If the pause length is an integer multiple of the clock period, then phase correction is minimal (at most one small error), but the pause length cannot accommodate variable durations

Engineering Contradiction:

Improvephase correction precisionVSAvoidpause length configuration

Core Design Contradiction:

Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent introduces an intermediary accumulator register that stores the fractional clock period value. This intermediary component bridges the gap between variable pause lengths and precise phase correction requirements. The accumulator holds the fractional value that represents the deviation from an integer multiple clock period, allowing the system to accommodate any pause duration while maintaining precise phase correction capability through the stored intermediary value.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7642821B2Method for synchronizing a clock signal with a reference signal, and phase locked loop

Publication Date: 2010.01.05 INFINEON TECHNOLOGIES AG

AI summary

A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period. The method includes generating a phase difference signal which is proportional to a phase difference between the clock signal and the reference signal, filtering the phase difference signal and providing a filtered phase difference signal, driving a digital oscillator in such a manner that the frequency of the clock signal is changed on the basis of the filtered phase difference signal, the phase of the clock signal within a clock period being corrected by a value corresponding to the fraction of the clock period at an end of the pause in the reference signal.