Multi-Loop Digital PLL for TDC Calibration and Metastability Control
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Solution Overview
Problem
Digital phase locked loop (DPLL) circuits face challenges in achieving accurate phase locking and minimizing noise in high-frequency clock signals due to limitations in time-to-digital converter (TDC) performance and metastability issues, particularly in multi-feedback loop configurations.
Innovation Solution
The implementation of a DPLL circuit with multiple digital feedback loops, a TDC module for phase error measurement, a digitally controlled oscillator (DCO), and a calibration circuit to adjust TDC parameters, along with a supervisor circuit to mitigate metastability, ensures accurate phase locking and reduced noise by calibrating TDC outputs and adjusting feedback signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a time-to-digital converter (TDC) is used to measure phase difference in a DPLL, then phase locking capability is improved, but measurement precision deteriorates due to TDC performance limitations
Solution Approach 1:
The patent divides the single feedback loop into multiple feedback loops (first feedback loop with TDC for phase error and second feedback loop for frequency error), allowing each loop to specialize in specific measurements and reduce the burden on the TDC, thereby improving overall measurement precision while maintaining phase locking capability
Solution Approach 2:
The patent introduces a digital filter as an intermediary between the TDC output and the DCO control, and adds a frequency detection mechanism as another intermediary layer. These intermediaries process and refine the TDC measurements, compensating for TDC limitations and improving phase difference measurement precision
2Measurement precision
If multiple digital feedback loops are implemented, then phase locking accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of phase detection and frequency detection into a unified DPLL architecture where both feedback loops share common components such as the DCO, reference clock source, and digital filter. This merging approach improves phase locking accuracy through multiple loops while minimizing the increase in overall circuit complexity by reusing existing blocks
3Measurement precision
If calibration circuit is added to adjust TDC parameters, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The calibration circuit performs preliminary adjustment of TDC parameters during device initialization or manufacturing test phases. By pre-calibrating the TDC to compensate for process variations and mismatches before normal operation, the system achieves high measurement precision without requiring complex real-time calibration mechanisms during operation
Data Source
AI summary
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.