Digital PLL Architecture Using TDC and Integer Divider for Low Power
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Solution Overview
Problem
Conventional analog Phase Locked Loops (PLLs) in wireless communication systems face challenges with high power consumption, large area occupancy, and increased manufacturing costs due to sensitivity to process characteristics and the need for redesign when scaled down, along with complexity in divider circuits and power consumption issues related to fractional PLLs.
Innovation Solution
A digital Phase Locked Loop (PLL) is implemented with a Digitally Controlled Oscillator (DCO), a divider operating at an integer ratio, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler, which reduces area and power consumption by eliminating the need for fractional dividers and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog PLL is used, then the PLL can operate at high speed, but the area occupied by the PLL becomes large and power consumption increases
Solution Approach 1:
The patent replaces the analog PLL system with a digital PLL system, substituting analog components (VCO, analog dividers, loop filter with passive R and C) with digital components (DCO, digital dividers, digital loop filter). This substitution dramatically reduces the area occupied by the PLL while maintaining high-speed operation capability, as digital circuits can be implemented more compactly using standard digital logic cells and registers.
Solution Approach 2:
The patent changes the operating parameters of the PLL by using a digital architecture that allows flexible parameter control through digital tuning words. The DCO can be tuned digitally, and the dividers can operate at various frequencies controlled by digital signals, enabling high-speed operation without requiring large analog component values that would increase area.
2Measurement precision
If an analog PLL is used, then the PLL can maintain accurate signal levels, but power consumption becomes very large
Solution Approach 1:
The patent replaces the analog signal level detection and control system with a digital system. The PFD detects phase differences and converts them to digital signals, which are then processed by digital logic circuits. This digital substitution eliminates the need for multiple analog buffers (VCO buffer, LO buffer, output buffer) that consume significant power, while maintaining precise signal level control through digital logic levels.
Solution Approach 2:
The patent extracts and removes the power-consuming analog buffer stages from the PLL system. By using a digital architecture, the system eliminates the need for multiple voltage-level buffering stages that are required in analog PLLs to maintain signal integrity, thereby significantly reducing power consumption while preserving signal level accuracy through digital logic.
3Area of stationary object
If an analog PLL is scaled down, then the area is reduced, but redesign is required and manufacturing costs increase
Solution Approach 1:
The patent replaces the analog PLL with a digital PLL, where the core functionality is implemented using digital logic circuits that are standard in modern semiconductor manufacturing. Digital circuits are less sensitive to process variations and can be manufactured using standard CMOS processes without requiring redesign when scaling. The digital architecture allows the same circuit topology to be manufactured across different process nodes and technologies, improving ease of manufacture and reducing costs.
4Adaptability or versatility
If a fractional PLL is used, then the channel interval and PLL bandwidth problems are solved, but the divider circuit becomes complicated and power consumption increases
Solution Approach 1:
The patent replaces the complex analog fractional divider circuitry with a digital implementation. The digital loop filter and digital control logic can implement fractional division ratios through digital signal processing and accumulation techniques, avoiding the need for complex analog switching and timing circuits. This digital approach maintains the ability to control channel intervals and PLL bandwidth while significantly simplifying the divider circuit architecture and reducing power consumption.
Data Source
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AI summary
A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.