Digital PLL Timing Measurement for Low-Power Wireless Frequency Control
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Solution Overview
Problem
Conventional analog Phase Locked Loops (PLLs) in wireless communication systems face challenges with high power consumption, large area occupation, and increased manufacturing costs due to their analog nature, which becomes exacerbated when scaled down, and they require complex redesigns for process changes, leading to inefficiencies in noise handling and accuracy.
Innovation Solution
A digital Phase Locked Loop (PLL) is implemented using a Digitally Controlled Oscillator (DCO), a divider for integer ratio frequency division, a Phase Frequency Detector (PFD) for phase difference measurement, a Time to Digital Converter (TDC) for precise time interval measurement, a delay comparator for calculating time intervals, and a level scaler to generate digital tuning words, reducing area and power consumption while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog PLL is used, then the PLL can operate at high speed, but the area occupied by the PLL becomes large and power consumption increases
Solution Approach 1:
The patent replaces the analog PLL system with a digital PLL system, substituting analog components (VCO, loop filter, buffers) with digital components (DCO, digital loop filter, logic circuits). This substitution dramatically reduces the area occupied by the PLL while maintaining high operating speed through digital signal processing techniques.
Solution Approach 2:
The patent changes the operating parameters by using a digital domain approach instead of analog. The DCO uses digital tuning words to control frequency, and the time-to-digital converter measures phase differences in the digital domain, enabling high-speed operation with reduced area compared to analog implementations.
2Power
If an analog PLL is used, then the PLL can generate carrier signals, but power consumption becomes very large
Solution Approach 1:
The patent replaces power-hungry analog components with low-power digital components. The DCO consumes less power than analog VCOs, the digital loop filter eliminates the need for power-intensive analog filters, and the integer divider is more power-efficient than fractional dividers, collectively achieving carrier signal generation with significantly reduced power consumption.
3Adaptability or versatility
If a fractional PLL is used to address channel interval issues, then the PLL bandwidth can be adjusted, but the divider circuit becomes complicated and area increases
Solution Approach 1:
The patent extracts and removes the complex fractional divider and sigma-delta modulator from the PLL architecture. By using an integer divider with a simplified structure and adjusting the DCO frequency directly, the patent achieves PLL bandwidth adjustment without the complexity and area overhead of fractional division circuits.
4Area of stationary object
If an analog PLL is scaled down, then the device size reduces, but the area cannot reduce remarkably due to current source requirements and noise issues
Solution Approach 1:
The patent replaces analog components that are sensitive to scaling and noise with digital components. The DCO maintains frequency accuracy without requiring large current sources, and the digital loop filter provides noise immunity, enabling significant area reduction while maintaining reliable noise performance even at scaled dimensions.
Data Source
AI summary
A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.