Digital Phase-Locked Loop for Low-Power Transmitter Integration
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Solution Overview
Problem
Existing phase locked loops (PLLs) in transmitter designs, particularly those based on analogue circuitry, face challenges in power consumption and complexity, making it difficult to implement digital forms of PLLs and amplitude modulators effectively.
Innovation Solution
A digital phase locked loop is designed with integrators, a filter, and a digital-to-analogue converter, where the loop filter and phase detector functions are performed in the digital domain, allowing for low power consumption and efficient integration with an amplitude modulator, using weighted signals and truncation units to maintain stability and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an analogue PLL design is used, then the transmitter can operate with acceptable power consumption, but the design complexity increases and integration with digital circuits becomes difficult
Solution Approach 1:
The patent replaces the traditional mechanical/analog phase detector and loop filter with digital circuitry. The phase detector uses digital logic to compare phases, and the loop filter is implemented as a digital filter, eliminating the need for analog components and enabling full integration with digital baseband processors.
Solution Approach 2:
The patent changes the operating domain from analog to digital by sampling the phase error signal and processing it through digital algorithms. This parameter change allows the PLL to be implemented using standard digital CMOS processes, improving manufacturability and integration while reducing sensitivity to process variations.
2Ease of manufacture
If a digital PLL design is used, then the transmitter achieves lower power consumption and easier integration, but implementing digital phase detectors and loop filters proves difficult in practice
Solution Approach 1:
The patent segments the PLL function into distinct digital blocks: a phase detector that samples phase error, a digital loop filter that processes the error signal, and a frequency control word generator. This segmentation makes the complex digital implementation manageable and allows each block to be optimized independently using standard digital design techniques.
Solution Approach 2:
The patent introduces a digital interface layer that mediates between the analog VCO output and the digital processing elements. Phase sampling circuits and digital-to-analog converters serve as intermediaries, enabling seamless integration between analog and digital domains while maintaining the benefits of digital processing.
3Measurement precision
If analogue circuitry is used in the PLL, then the phase comparator can meet desired tolerances, but power consumption increases
Solution Approach 1:
The patent uses periodic sampling of the phase error signal at specific instants when the reference and VCO signals are known to be in specific states. This periodic sampling approach achieves accurate phase detection using simple digital logic instead of continuous analog comparison, significantly reducing power consumption while maintaining precision.
Solution Approach 2:
The patent replaces expensive, power-hungry analog phase comparators with inexpensive digital logic circuits that consume minimal power. The digital phase detection uses simple logic operations that can be implemented with minimal transistor count, achieving the required precision at a fraction of the power cost of analog implementations.
Data Source
AI summary
A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.