Digital PLL Two-Point Modulation With Adaptive Path Delay Matching
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Solution Overview
Problem
Existing digital phase-locked loops (DPLLs) face performance degradation when using two-point modulation due to mismatched delays in highpass and lowpass modulation paths, which can lead to suboptimal modulation of wideband signals without disturbing normal DPLL operation.
Innovation Solution
A DPLL with adaptive delay matching, incorporating an adaptive delay unit that dynamically adjusts the delay of one modulation path to match the other, using a delay computation unit, interpolator, and programmable delay unit to ensure proper delay alignment, and an adaptive scaling unit to match the gain of both paths, allowing for effective wideband and narrowband modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two-point modulation is used to increase DPLL bandwidth for wideband modulation, then the modulation bandwidth is improved, but performance degradation occurs due to mismatched delays in highpass and lowpass modulation paths
Solution Approach 1:
The patent implements dynamic delay adjustment in the highpass modulation path using an adaptive delay unit that can vary its delay value based on the actual delay mismatch detected between the two modulation paths. This dynamic adaptation allows the system to maintain optimal performance across different operating conditions while supporting wideband modulation through two-point modulation.
Solution Approach 2:
The patent employs a feedback mechanism where the delay mismatch between the lowpass and highpass modulation paths is measured and used to control the adaptive delay unit. The delay computation unit calculates the mismatch based on phase error signals, and this information feeds back to adjust the delay in the highpass path, creating a closed-loop system that automatically compensates for delay differences.
2Device complexity
If fixed delay is used in modulation paths, then device complexity is reduced, but modulation performance degrades due to inability to compensate for delay mismatch
Solution Approach 1:
The patent replaces fixed delay structures with dynamic, adaptive delay units that can adjust their delay values based on actual mismatch conditions. The adaptive delay unit includes a delay computation unit, interpolator, and programmable delay unit that work together to provide dynamically adjusted delay compensation, improving performance without requiring overly complex structures.
Solution Approach 2:
The patent changes the delay parameter in the highpass modulation path dynamically based on detected mismatch conditions. The delay computation unit calculates the required delay adjustment, and the programmable delay unit implements this parameter change, allowing the system to adapt to varying conditions while maintaining manageable complexity.
3Reliability
If adaptive delay matching is implemented, then modulation performance is improved, but device complexity increases due to additional delay computation and interpolation units
Solution Approach 1:
The patent segments the adaptive delay unit into distinct functional blocks: a delay computation unit that calculates the required delay adjustment, an interpolator that generates the appropriate delay value, and a programmable delay unit that implements the adjustment. This segmentation allows each component to be optimized independently and simplifies the overall design while achieving the desired performance improvement.
Solution Approach 2:
The patent introduces an interpolator as an intermediary component between the delay computation unit and the programmable delay unit. The interpolator processes the computed delay value and generates appropriate control signals for the programmable delay unit, acting as a mediator that simplifies the interface between computation and implementation while enabling fine-grained delay control.
4Ease of operation
If delay mismatch exists between modulation paths, then normal DPLL operation is maintained, but wideband modulation performance is suboptimal
Solution Approach 1:
The patent implements a feedback mechanism where the phase error signal is used to compute the delay mismatch between modulation paths. This mismatch information feeds back to the adaptive delay unit, which adjusts its delay to compensate for the difference. This closed-loop feedback allows the system to maintain stable normal operation while simultaneously optimizing wideband modulation performance through automatic delay matching.
Solution Approach 2:
The patent enables the DPLL system to self-correct for delay mismatch through its own internal signals. The phase error signal generated during normal DPLL operation is reused to compute and adjust the delay in the highpass modulation path, allowing the system to serve itself and eliminate the need for external calibration or additional complex control mechanisms.
Data Source
AI summary
A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.