Digital PLL Acquisition Using Tuning-Voltage Window Control
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Solution Overview
Problem
Existing frequency synthesizers face challenges in rapidly changing frequencies while maintaining low phase noise, especially at large frequency offsets, and require a high component count and complex control systems to operate effectively over a wide temperature range.
Innovation Solution
A signal generator with a digitally controlled phase-locked loop (PLL) system that uses a memory to store tuning voltage and offset voltage values, an adder/subtractor circuit, a comparator circuit, and a steering current circuit to rapidly adjust the frequency by comparing the actual tuning voltage to a window bounded by the sum and difference of these values, thereby controlling the steering current to achieve precise frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop bandwidth is increased to achieve fast frequency tuning, then the tuning speed is improved, but the phase noise at large frequency offsets from the carrier is degraded
Solution Approach 1:
The patent pre-calculates and stores optimal tuning voltage values and offset voltage values in a memory for different frequency offsets before operation. During frequency tuning, the system rapidly retrieves these pre-computed values and applies them through adder/subtractor circuits to generate the required tuning signals, enabling fast frequency changes without requiring wide loop bandwidth that would degrade phase noise performance.
2Object-generated harmful factors
If the loop bandwidth is decreased to maintain low phase noise, then the phase noise performance is improved, but the tuning time is increased
Solution Approach 1:
The system performs preliminary calculations of tuning voltages and offset voltages for various frequency offsets and stores them in memory. During operation, these pre-computed values are rapidly retrieved and processed through adder/subtractor circuits, enabling the PLL to achieve fast frequency acquisition times while maintaining a narrow loop bandwidth for low phase noise performance.
Solution Approach 2:
The patent replaces the traditional analog voltage generation method with a digital signal processing approach. Digital values for tuning voltages and offset voltages are stored in memory, retrieved, and processed through digital adder/subtractor circuits to generate the required analog tuning signals. This substitution enables rapid frequency changes without requiring wide analog loop bandwidth.
3Adaptability or versatility
If a wide temperature range operation is required, then the adaptability is improved, but the component count and system complexity are increased
Solution Approach 1:
The patent implements a universal frequency tuning system where the same memory, adder/subtractor circuits, and control logic handle both frequency offset compensation and temperature compensation functions. The system stores and processes tuning voltage values and offset voltage values that account for both frequency and temperature variations, eliminating the need for separate compensation circuits and reducing overall system complexity.
Solution Approach 2:
The system compensates for temperature variations by changing the stored tuning voltage values and offset voltage values in memory based on temperature conditions. The digital signal processing circuits process these updated values to generate appropriate tuning signals, allowing the PLL to maintain accurate frequency control across a wide temperature range without requiring additional analog compensation components.
Data Source
AI summary
Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.