Digital Fractional PLL Architecture Without Sigma-Delta Spurs
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Solution Overview
Problem
Conventional fractional phase-locked loops (PLLs) introduce quantization noise and generate fractional spurs due to the use of sigma delta modulators, which increase the in-band noise floor and degrade phase noise performance.
Innovation Solution
The implementation of a digital fractional PLL architecture that includes a digital voltage controlled oscillator (DVCO), an integer divider, a phase/frequency detector, a time-to-digital converter (TDC), a digital accumulator block, and a digital loop filter, which eliminates sigma delta modulators and merges the DVCO and TDC into a single digital timing block, reducing noise and spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sigma delta modulator is used in a conventional fractional PLL to achieve fractional division ratio, then the feedback ratio can be precisely controlled, but quantization noise is introduced and fractional spurs are generated, degrading phase noise performance
Solution Approach 1:
The patent extracts and removes the sigma delta modulator from the PLL architecture, replacing it with a digital accumulator that directly generates the fractional division ratio without introducing quantization noise or fractional spurs. This extraction eliminates the harmful quantization effects while preserving the fractional division capability.
Solution Approach 2:
The patent uses a digital accumulator to copy and accumulate the fractional division ratio value, creating a noise-free digital representation that can be directly used by the integer divider. This digital copying approach avoids the analog quantization processes that generate noise and spurs.
2Adaptability or versatility
If a sigma delta modulator is used to generate fractional feedback signal, then the division ratio can be varied continuously, but the in-band noise floor increases
Solution Approach 1:
The patent replaces the analog sigma delta modulator mechanism with a digital accumulator and integer divider system. This substitution transitions from analog modulation (which introduces noise) to digital accumulation (which is noise-free), thereby maintaining division ratio variability without increasing the in-band noise floor.
3Reliability
If separate DVCO and TDC blocks are used in digital fractional PLL, then phase detection and control functions are implemented, but circuit complexity and power consumption increase
Solution Approach 1:
The patent merges the separate DVCO (digital voltage controlled oscillator) and TDC (time-to-digital converter) blocks into a single integrated digital oscillator unit. This consolidation eliminates redundant circuitry and interfaces between the two blocks, reducing both circuit complexity and power consumption while maintaining the essential phase detection and control functions.
Data Source
AI summary
A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.