Digital PLL Feedback Divider Layout for Pseudo Zero Delay
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Solution Overview
Problem
Conventional phase-locked loops face challenges in achieving zero delay while maintaining noise performance, particularly when using fractional frequency dividers, which can lead to misalignment of the output phase with the input reference signal.
Innovation Solution
A pseudo zero delay digital phase-locked loop (DPLL) is implemented, incorporating a fractional frequency divider and multiple dividers, including a post divider, channel divider, and feedback divider, with time-to-digital converters (TDCs) to determine phase differences, and an averager circuit to reduce noise, ensuring the output frequency is phase-aligned with the input reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional frequency divider is used to achieve pseudo zero delay, then the output phase alignment with input reference signal is improved, but noise performance deteriorates
Solution Approach 1:
The feedback path is segmented into multiple dividers (first divider, second divider, third divider) with different division ratios. This segmentation allows the system to achieve pseudo-zero delay through coordinated operation of multiple integer dividers while avoiding the noise issues of fractional dividers. Each divider operates at integer ratios, maintaining signal integrity while collectively achieving the desired phase alignment.
Solution Approach 2:
Instead of using a fractional frequency divider to achieve phase alignment (which causes noise), the invention inverts the approach by using multiple integer frequency dividers with carefully selected division ratios. The inverted approach achieves the same pseudo-zero delay effect through integer divisions, thereby eliminating the noise performance degradation while maintaining phase alignment accuracy.
2Object-affected harmful factors
If multiple dividers are used to maintain noise performance, then noise performance is improved, but device complexity increases
Solution Approach 1:
The multiple dividers in the feedback path serve multiple functions simultaneously: they establish the pseudo-zero delay condition, maintain integer ratio relationships for noise performance, and enable flexible frequency synthesis. This multi-functionality reduces the need for separate circuits for each purpose, thereby limiting the increase in overall device complexity despite using multiple divider stages.
3Object-affected harmful factors
If integer frequency dividers are used instead of fractional dividers, then noise performance is improved, but phase alignment accuracy deteriorates
Solution Approach 1:
The system dynamically coordinates the operation of multiple integer dividers with different division ratios to achieve pseudo-zero delay. By dynamically adjusting and coordinating the division ratios among the first, second, and third dividers, the system achieves accurate phase alignment using only integer divisions, thereby maintaining noise performance while improving phase alignment accuracy compared to static integer divider approaches.
Solution Approach 2:
The multiple dividers operate in a feedback loop where the output of the last divider feeds back to the input of the first divider. This feedback mechanism enables the system to maintain precise phase alignment by continuously adjusting the division ratios to achieve pseudo-zero delay, while all dividers operate at integer ratios to preserve noise performance.
Data Source
AI summary
A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.