Digital Power Estimation Network for Proactive AI Chip Clock Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ML/AI processor designs rely on reactive thermal and current sensor readings for power management, which are slow and unreliable, leading to performance reductions and system instability due to delayed responses.
Innovation Solution
Implementing a power base unit (PBU) with switch, memory, and compute estimators (SPE, MPE, CPE) that digitally communicate power estimates via a dedicated network to a power estimation unit (PEU), allowing for rapid, accurate prediction of dynamic and static power usage, enabling proactive power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional thermal sensor and current sensor readings are used for power management, then power management can be implemented, but the response time is slow (milliseconds) and the system becomes unreliable
Solution Approach 1:
The patent segments power estimation into three independent estimator modules: switch power estimator (SPE), memory power estimator (MPE), and compute power estimator (CPE). Each estimator independently calculates power consumption for its specific component type, and their results are combined to obtain total power estimation. This segmentation enables parallel processing of power estimates from different components, achieving high-speed response while maintaining accurate and reliable power management.
2Reliability
If reactive power management based on sensor readings is used, then power monitoring is possible, but performance must be reduced to maintain system reliability
Solution Approach 1:
The patent implements preliminary action by proactively estimating power consumption using SPE, MPE, and CPE before thermal issues actually occur. The system continuously monitors and predicts power usage trends, enabling power management decisions to be made in advance rather than reactively. This allows the system to maintain high performance while ensuring reliability through ahead-of-time power awareness.
Solution Approach 2:
The patent establishes a feedback mechanism where power estimates from SPE, MPE, and CPE are continuously fed to the power clock management controller (PCMC). The PCMC uses this feedback to dynamically adjust clock frequencies and supply voltages, creating a closed-loop control system that maintains optimal performance while preventing power-related failures.
3Measurement precision
If thermal sensor readings with millisecond measurement time are used, then power management is achievable, but the measurement precision and response bandwidth are insufficient
Solution Approach 1:
The patent replaces the mechanical/physical thermal sensor measurement system with a digital computational estimation system. Instead of physically measuring temperature and inferring power consumption (which is slow), the system uses digital estimators (SPE, MPE, CPE) that calculate power consumption directly from operational parameters. This substitution achieves both high measurement precision and extremely fast response times, eliminating the millisecond delay inherent in thermal sensing.
Data Source
AI summary
An integrated circuit (IC) comprises an array of power base units (PBUs) organized in rows and columns. The IC further includes an array-level power accumulator that includes a power estimation unit (PEU) and two or more column power accumulators (CPAs) coupled with the PEU and the PBUs via dedicated wiring. Additionally, a power clock management controller (PCMC) is linked to the array-level power accumulator. Notably, some CPAs are connected to the array-level power accumulator through dedicated wiring.