Differential Digital Power Amplifier With Driver Current Reuse
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Solution Overview
Problem
Differential digital power amplifiers used in RFID antennas face efficiency losses due to the need for intermediate power supplies in small geometry semiconductor processes, particularly when using extended drain MOS transistors, which are inefficient and consume significant power in battery-powered devices.
Innovation Solution
A differential digital power amplifier design that incorporates a switch between the high and low side driver voltages to create a voltage divider, allowing current reuse between PMOS and NMOS transistors, reducing driver current and increasing efficiency by reusing charge carriers from the high side driver for the low side driver, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If intermediate power supplies are used to drive gate voltages of extended drain MOS transistors, then the power amplifier can operate from a single supply voltage, but efficiency drops significantly due to power loss in internal pass devices
Solution Approach 1:
The patent merges the high side driver and low side driver power supply systems by introducing a bypass switch that connects the low side driver voltage to the high side driver voltage when the high side driver voltage exceeds the low side driver voltage by more than 0.5V. This allows the low side driver to reuse charge carriers from the high side driver, eliminating the need for separate intermediate power supplies and reducing power loss in internal pass devices.
Solution Approach 2:
The patent recovers charge carriers that would otherwise be discarded by the high side driver and reuses them in the low side driver through the bypass switch. This recovery mechanism prevents the charge carriers from being lost in the internal pass devices of separate power supplies, thereby improving efficiency while maintaining single supply voltage operation.
2Reliability
If separate pre-driver stages powered by voltage regulators are used for extended drain MOS transistors, then gate-source voltages can be kept below maximum allowed levels, but total driver current increases significantly
Solution Approach 1:
The patent combines the power supply paths of the high side driver and low side driver through the bypass switch, allowing them to share charge carriers. This merging reduces the total driver current from 64 mA to 42 mA while still maintaining proper gate-source voltage levels through the voltage follower circuitry that ensures voltages remain below maximum allowed levels.
Solution Approach 2:
The high side driver serves the low side driver by providing charge carriers through the bypass switch when voltage conditions are favorable. This self-service mechanism eliminates the need for separate power regulation for each driver stage, reducing total current consumption while maintaining reliable gate-source voltage control.
3Stability of the object's composition
If DC-DC convertors are used to create constant output voltage from variable battery voltage, then power amplifier voltage stability is improved, but efficiency decreases due to convertor power loss
Solution Approach 1:
The patent introduces dynamic voltage sharing between the high side and low side drivers through the bypass switch, which activates when the high side driver voltage exceeds the low side driver voltage by more than 0.5V. This dynamic mechanism allows the system to adapt to varying battery voltages without requiring a DC-DC convertor, maintaining voltage stability while avoiding convertor power losses.
Data Source
AI summary
A differential digital power amplifier to drive an RFID antenna with a sinusoidal output current with an RFID frequency which differential digital power amplifier comprises: a digital control section to output digital wave-forming bits to a first group of driver blocks and a second group of driver blocks wherein a switch between the source contact of a first source follower transistor and the source contact of a second source follower transistor to short circuit these source contacts to unload/load gate-source capacitances of a drain extended PMOS transistors with charge carriers used to load/unload gate-source capacitances of the drain extended NMOS transistors to reduce the driver current needed at gate contacts of the drain extended PMOS transistors and drain extended NMOS transistors.