Digital Power Source Circuit for DAC-Free DC Offset Cancellation

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Solution Overview

Problem

Existing power source circuits lack accurate control over output power levels, leading to issues like distortion and clipping in analog signal processing chains, which increases design complexity and silicon area, particularly in digital-to-analog converters (DACs) used for DC offset cancellation.

Innovation Solution

A power source circuit with a digital controller and a current generation circuit that includes switching devices and a capacitor, allowing for precise control of output current or voltage based on digital signals from a feedback loop, eliminating the need for complex DACs by using relative control inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a DAC is inserted in the analog signal processing chain to counter DC offset, then DC offset cancellation is achieved, but design complexity and silicon area significantly increase

Engineering Contradiction:
ImproveDC offset cancellation capabilityVSAvoiddesign complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the DC offset cancellation function into discrete current steps that can be independently controlled. Instead of using a complex DAC, the invention divides the cancellation current into multiple controllable segments that are switched in and out based on feedback, simplifying the overall design while maintaining effectiveness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of the current source through feedback mechanisms. The cancellation current is not fixed but is continuously adjusted based on the detected DC offset level, allowing the system to adapt to varying conditions without requiring a complex high-precision DAC.

Inventive Principle:
Principle #15Dynamics

2Reliability

If a DAC is inserted in the analog signal processing chain to counter DC offset, then DC offset cancellation is achieved, but silicon area significantly increases

Engineering Contradiction:
ImproveDC offset cancellation capabilityVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the essential function of DC offset cancellation from the complex DAC structure. By taking out only the necessary current control capability and implementing it through simpler switching and feedback mechanisms, the invention achieves the same cancellation effect with significantly reduced silicon area.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of implementing a full DAC, the patent creates a simplified copy of the essential current control function using feedback-driven switching. This approach replicates the necessary behavior of a DAC for DC offset cancellation without requiring the full complexity and area of a traditional DAC implementation.

Inventive Principle:
Principle #26Copying

3Reliability

If traditional DAC control is used, then DC offset cancellation is achieved, but strict monotonicity of the DAC input-output relation is required

Engineering Contradiction:
ImproveDC offset cancellation capabilityVSAvoidcontrol algorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional DAC control approach. Instead of requiring the control algorithm to enforce strict monotonicity on the DAC input-output relation, the invention uses feedback to directly control the cancellation current based on the detected offset, eliminating the monotonicity requirement and simplifying the control logic.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentEP2887273B1Digitally controllable power source
Publication Date: 2017.02.22 NXP BV
  • EP2887273B1 patent drawing
  • EP2887273B1 patent drawing
  • EP2887273B1 patent drawing

AI summary

A proximity integrated circuit card bias adjustment. In one example, a decoding circuit, having an decoding range, for translating a data-frame signal having an information portion and a bias portion into an output code; and a bias adjust circuit coupled to receive the output code from the decoding circuit, and adjust the bias portion of the data-frame signal such that the output code is within the decoding range is disclosed. In another example, a method for proximity integrated circuit card bias adjustment, comprising: translating a data-frame signal having an information portion and a bias portion into an output code; and adjusting the bias portion of the data-frame signal such that the output code is within a decoding range is disclosed.