Digital Pulse Processing for High Count Rate Energy Resolution
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Solution Overview
Problem
Current medical imaging devices face challenges with cumbersome reprogramming and adaptation of printed circuit boards processing analog pulses from PMT or APD detectors, high count rates leading to pulse pileup, and the need for improved energy and positioning performance while maintaining stability and reducing costs.
Innovation Solution
An event processing module comprising an ASIC with a Constant Fraction Discriminator, ADC, and FPGA, configured to continuously sample analog signals, determine energy by subtracting peak from baseline values, and detect pileup by comparing current baseline values to moving averages, allowing for digital pulse processing and efficient handling of high count rates without hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuously sampled digital pulse processing is implemented, then energy resolution and positioning accuracy are improved at high count rates, but device complexity increases due to ADC and FPGA requirements
Solution Approach 1:
The patent replaces traditional analog pulse processing electronics with a continuously sampled digital pulse processing system using ADC and FPGA. This substitution enables accurate energy measurement and pileup detection through digital signal processing, achieving superior energy resolution (10-15% at 511 keV) and positioning accuracy even at high count rates where analog systems fail.
Solution Approach 2:
The system changes the sampling rate parameter to 100 MHz (or higher) to capture pulse waveforms continuously, enabling flexible digital processing. This parameter change allows the system to handle high count rates by processing pulses in the digital domain, where pileup can be detected and rejected algorithmically rather than requiring complex analog timing circuits.
2Adaptability or versatility
If analog pulse processing circuits are used, then device complexity is reduced, but adaptability and reprogramming capability are worsened due to cumbersome hardware modifications
Solution Approach 1:
The patent replaces fixed analog pulse processing circuits with a programmable digital system based on FPGA. This allows the processing algorithms to be reconfigured through software updates rather than hardware modifications, providing excellent adaptability for different imaging protocols and analysis methods while maintaining relatively simple hardware architecture.
Solution Approach 2:
The continuously sampled digital system serves multiple functions: energy measurement, timing extraction, pileup detection, and waveform analysis. The same ADC and FPGA infrastructure supports various processing algorithms and imaging modes, making the system universally applicable across different clinical and research applications without requiring separate dedicated circuits for each function.
3Productivity
If high count rates are processed, then productivity is improved, but measurement precision deteriorates due to pulse pileup effects
Solution Approach 1:
The patent uses digital pulse processing to detect and reject pileup events that occur at high count rates. The continuously sampled waveforms allow the system to identify overlapping pulses through digital analysis, maintaining accurate energy measurement and coincidence detection even when processing high rates of annihilation events, thereby preserving measurement precision while achieving high productivity.
Solution Approach 2:
The system employs feedback mechanisms where the digitized pulse waveforms are analyzed to detect pileup conditions, and this information feeds back into the event acceptance decision. When pileup is detected, the system can reject the affected events or apply correction algorithms, ensuring that only valid coincidence events are histogrammed, thus maintaining measurement precision at high count rates.
4Measurement precision
If baseline subtraction method is used for energy determination, then measurement precision is improved, but device complexity increases due to continuous sampling requirements
Solution Approach 1:
The patent implements baseline subtraction for energy determination using the continuously sampled digital waveforms from the ADC. The FPGA extracts the baseline level and pulse peak from the digitized signal, subtracts them to obtain the pulse height, and uses this for energy measurement. This digital approach provides superior energy determination accuracy compared to analog methods while the increased complexity is offset by the versatility and reprogrammability of the digital system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate energy and positioning resolution at high count rates, facilitates easy reprogramming, reduces pileup issues, and maintains stability, thus improving the performance and cost-effectiveness of medical imaging devices with large block detectors.
Implementation Method 1
A trigger is generated when the pulse exceeds a threshold set by a Constant Fraction Discriminator (CFD)
Implementation Method 2
The analog outputs are continuously sampled using an Analog to Digital Converter (ADC) and digital outputs transmitted
Implementation Method 3
determine the energy of the analog signals from the at least one PMT by subtracting the peak value of each signal from the baseline value of each signal
Implementation Method 4
detect pileup by comparing current baseline values to moving averages
Data Source
AI summary
A method for processing events in a medical imaging device may comprise the steps of receiving analog signals from at least one PMT into an Applied Specific Integrated Circuit (ASIC) comprising a Constant Fraction Discriminator (CFD) and transmitting analog outputs from the ASIC. Further, sampling the analog outputs continuously using an Analog to Digital Converter (ADC) and transmitting digital outputs; and collecting a number of samples of the digital output during a sampling period using a Field Programmable Gate Array (FPGA) when triggered by the CFD. The method may additionally determine the energy of the analog signals from the at lease one PMT by subtracting the peak value of each signal from the baseline value of each signal, wherein the peak value is determined as an average of at least one sample taken only around the peak during the sampling period, and the baseline value is determined as an average of at least one sample taken only around the beginning or end of the sampling period.