Multi-Phase Digital Pulse Width Generation for High-Resolution Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog pulse width generators have large area requirements and long response times, necessitating redesigns for different fabrication processes, which motivates the development of digital pulse width generators for improved performance.
Innovation Solution
A digital pulse width generator comprising a phase control circuit and a phase select circuit, utilizing multi-phase clock signals to generate and select pulse width signals based on bit sets of pulse data, enabling high-resolution and high-linearity digital pulse width signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog circuits are used to implement pulse width generators, then the circuit can be designed with continuous signal processing, but the area occupied is large and response time is long
Solution Approach 1:
The patent replaces analog circuit implementation with digital circuit implementation. Specifically, it uses digital counters, phase selection logic, and digital signal processing to generate PWM signals, substituting the continuous analog signal processing with discrete digital operations. This substitution reduces circuit area while maintaining signal generation precision through binary-coded pulse width control.
Solution Approach 2:
The patent segments the pulse width generation process into discrete digital stages: counter initialization based on input data, phase clock signal generation with different phases, phase selection based on counter values, and output signal generation. This segmentation allows each stage to be implemented with compact digital logic components rather than large analog circuits.
2Measurement precision
If analog circuits are used to implement pulse width generators, then the circuit can process continuous signals, but the response time is long
Solution Approach 1:
The patent replaces analog circuit implementation with digital circuit implementation. Specifically, it uses digital counters, phase selection logic, and digital signal processing to generate PWM signals, substituting the continuous analog signal processing with discrete digital operations. This substitution reduces circuit area while maintaining signal generation precision through binary-coded pulse width control.
Solution Approach 2:
The patent implements preliminary action by pre-generating multiple phase clock signals with different phases (e.g., 4-phase, 8-phase clocks) before the actual pulse width generation is needed. The counter is initialized with the desired pulse width value in advance, and the phase selection logic is prepared to select from pre-generated phase signals. This preliminary preparation enables faster response time when the actual PWM signal generation is triggered.
3Measurement precision
If analog pulse width generators are used, then the circuit can generate pulse width signals, but the circuit needs to be re-designed for different fabrication processes
Solution Approach 1:
The patent replaces analog circuit implementation with digital circuit implementation. Specifically, it uses digital counters, phase selection logic, and digital signal processing to generate PWM signals, substituting the continuous analog signal processing with discrete digital operations. This substitution reduces circuit area while maintaining signal generation precision through binary-coded pulse width control.
Solution Approach 2:
The patent achieves universality by designing a digital pulse width generator that can operate across different fabrication processes without redesign. The digital logic components (counters, phase selectors, multiplexers) are implemented using standard cell libraries that are process-agnostic. The same architectural design and logic equations can be synthesized for different CMOS processes (e.g., 65nm, 45nm, 28nm) by simply adjusting timing parameters and clock frequencies, eliminating the need for analog circuit redesign.
Data Source
AI summary
A digital pulse width generator and a method for generating a digital pulse width are provided. The method for generating a digital pulse width includes the following. Generating a first period according to first set of bits of pulse data. The first period includes an interval. First phase signals are set to a first logic value in the interval and are generated according to first phase clock signals after an end of the interval. Second phase signals are set to the first logic value in the first period and are generated according to second phase clock signals after an end of the first period. Selecting a first signal from the first phase signals and the second phase signals according to second set of bits of the pulse data as a pulse width signal.


