Digital PWM Controller with Analog Feed-Forward for Fast Dynamic Response
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Solution Overview
Problem
Conventional digital controllers for power converters suffer from phase lagging due to sampling effects and control delays, leading to degraded dynamic performance and high power consumption, especially when trying to achieve high-frequency and high-resolution PWM designs.
Innovation Solution
A digital PWM controller that introduces a feed-forward control in the analog domain using an input voltage-controlled ramp, minimizes sampling effects and control delays by converting the digital duty cycle signal to an analog signal for comparison with a ramp signal, and employs a windowed ADC and DAC with fewer bits to reduce die size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high clock frequencies are used to achieve high-frequency and high-resolution DPWM, then PWM resolution and switching frequency are improved, but power consumption increases to intolerable levels
Solution Approach 1:
The patent segments the PWM generation process into two independent parts: a digital PID controller operating at low clock frequency (e.g., 1 MHz) that calculates duty cycle values, and an analog PWM generator operating at high switching frequency (e.g., 100 kHz) that generates the actual PWM signal. This segmentation allows the digital portion to use lower clock frequencies reducing power consumption, while the analog portion maintains high-frequency operation for high-resolution PWM output.
2Extent of automation
If digital control algorithms are used to determine duty-cycle, then digital controller advantages are maintained, but phase lagging occurs due to sampling effect and control delays
Solution Approach 1:
The patent introduces an analog derivative circuit as an intermediary between the digital PID controller and the analog PWM generator. This analog derivative circuit processes the duty cycle signal to predict future error trends and generates a compensating signal that counteracts the phase lagging caused by digital sampling and control delays, thereby improving dynamic response without sacrificing digital control advantages.
3Extent of automation
If conventional digital PWM architecture is used, then digital controller advantages are maintained, but limit cycle oscillations occur due to quantization effects
Solution Approach 1:
The patent uses an analog derivative circuit as an intermediary that processes the duty cycle signal to predict future error trends and generates a compensating signal that counteracts the phase lagging caused by digital sampling and control delays, thereby improving dynamic response without sacrificing digital control advantages.
Solution Approach 2:
The patent changes the resolution parameter of the DPWM from conventional low-resolution digital values to high-resolution analog-equivalent values generated by the analog PWM circuit. This parameter change allows the system to achieve fine resolution (e.g., 16-bit or higher) without being constrained by digital quantization levels, thereby eliminating limit cycle oscillations while maintaining digital control capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances dynamic performance, eliminates limit cycle oscillations, and decreases power consumption while maintaining high-frequency operation, achieving improved bandwidth and reduced die size without increasing the system clock frequency.
Implementation Method 1
a comparator circuit for comparing a first signal including the DAC output signal with a reference signal for generating a pulse width modulated control signal
Implementation Method 2
a Digital to Analog Converter (DAC) circuit for converting the digital duty cycle signal into an analog DAC output signal
Implementation Method 3
an Analog to Digital Converter (ADC) circuit for digitizing inputted state variables including a feedback voltage from an output of the voltage converter and a reference voltage
Data Source
AI summary
A pulse width (PWM) controller for a voltage converter having at least one switch, an Analog to Digital Converter (ADC) circuit for digitizing inputted state variables including a feedback voltage from an output of the voltage converter and a reference voltage for setting the output of the voltage converter and providing a digital error signal, and a Proportional Integration and Derivation (PID) circuit receiving the digital error signal and providing a digital duty cycle signal. The controller including a Digital to Analog Converter (DAC) circuit for converting the digital duty cycle signal into an analog DAC output signal; and a comparator circuit for comparing a first signal including the DAC output signal with a reference signal for generating a pulse width modulated control signal for controlling the switching of the at least one switch of the voltage converter.