Digital PWM Pulse Position Compensation for Low-Clock Modulation
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Solution Overview
Problem
Digital PWM generation in smaller process node geometries faces challenges due to analogue circuitry design limitations, including distortion from quantization of pulse position and the need for fast clock speeds, which can impact the scalability and power efficiency of digital PWM modulators.
Innovation Solution
A PWM modulator with a pulse position controller that synchronizes pulse positions within the PWM cycle period, using an error block, loop filter, and quantizer to compensate for positional errors, allowing for efficient generation of pulses with both odd and even durations, thereby reducing timing errors and maintaining resolution without increasing clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital PWM generation uses fast clock speeds to avoid quantization distortion, then measurement precision is improved, but use of energy increases and device complexity worsens
Solution Approach 1:
The patent changes the parameter of clock frequency from high to low, and introduces a pulse position error compensation mechanism. By using a slow clock and compensating for quantization errors through feedback control, the system achieves high pulse position accuracy without requiring fast clock speeds, thereby reducing power consumption.
Solution Approach 2:
The patent implements a feedback loop that detects pulse position errors caused by quantization and compensates for them in subsequent cycles. The error detector measures the deviation from the ideal pulse position, and this error information is used to adjust the pulse generation timing, maintaining high precision without fast clocks.
2Measurement precision
If digital PWM generation uses fast clock speeds to avoid quantization distortion, then measurement precision is improved, but device complexity worsens
Solution Approach 1:
The patent changes the clock frequency parameter from high to low, which simplifies the timing circuit requirements. By compensating for quantization errors through a feedback mechanism rather than using fast clocks, the system reduces the complexity of the PWM generation circuit while maintaining high pulse position accuracy.
Solution Approach 2:
The feedback-based error compensation mechanism replaces the need for high-speed timing circuits. The error detector and compensator work together to correct quantization errors, allowing the use of simpler, lower-frequency clock circuits while achieving the same pulse position accuracy that would otherwise require complex high-speed circuitry.
3Manufacturing precision
If analogue circuitry is used for PWM modulation in smaller process node geometries, then manufacturing precision is improved, but ease of manufacture worsens
Solution Approach 1:
The patent replaces analogue circuitry with digital circuitry for PWM generation. By using digital logic elements (flip-flops, counters, logic gates) instead of analogue components, the system achieves manufacturability on smaller process nodes while maintaining PWM functionality. The digital implementation is more scalable and easier to manufacture in modern CMOS processes.
4Ease of operation
If pulse position is quantized to clock edges, then ease of operation is improved, but measurement precision worsens
Solution Approach 1:
The patent maintains simple clock-edge-aligned pulse generation while adding a feedback loop that detects and compensates for position errors. The error detector measures the deviation of quantized pulse positions from ideal positions, and the compensator adjusts subsequent pulse timing to correct these errors, preserving both operational simplicity and position accuracy.
Solution Approach 2:
The patent changes the approach from relying solely on fast clock timing to using slow clock timing with error compensation. By modifying the control strategy to include feedback-based correction, the system achieves high pulse position accuracy while maintaining the simplicity of clock-edge-aligned pulse generation.
Data Source
AI summary
This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.