Digital Ramp Signal Circuit With Parallel Interpolation
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Solution Overview
Problem
Existing electronic circuits struggle to provide digital signals with precise ramps at high frequencies using a clock signal with lower frequency, limiting the flexibility and accuracy of ramp modifications.
Innovation Solution
An electronic circuit configured to store ramp data in multiple memories, allowing parallel reading and interpolation to generate multiple digital values per clock cycle, using polynomial functions for slope calculation and batch processing to achieve precise ramp generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an electronic circuit is clocked by a clock signal at a frequency lower than the desired granularity of the digital signal, then the device complexity is reduced, but the manufacturing precision and time precision of the digital signal deteriorate
Solution Approach 1:
The patent divides the generation of multiple digital values into parallel segments by implementing Nout interpolation circuits that operate simultaneously. Each interpolation circuit generates one digital value based on ramp parameters (start value, slope, duration) stored in memory, allowing the circuit to produce Nout digital values in parallel within a single clock cycle, thereby achieving high time precision without requiring a high-frequency clock signal.
Solution Approach 2:
The patent pre-stores ramp parameters (start value, slope, and remaining duration) in memory before the actual signal generation. This preliminary storage of critical parameters allows the interpolation circuits to quickly compute multiple digital values without real-time calculations, enabling precise ramp generation even when clocked at lower frequencies.
2Device complexity
If the electronic circuit provides only one digital value per clock cycle, then the device complexity is reduced, but the productivity of digital signal generation deteriorates
Solution Approach 1:
The patent segments the digital signal generation process into Nout parallel interpolation circuits, where each circuit independently computes one digital value based on the stored ramp parameters. This parallel segmentation enables the circuit to output Nout digital values simultaneously in each clock cycle, dramatically increasing productivity while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The interpolation circuits are designed as universal computing units that can handle multiple ramp parameters (start value, slope, duration) using the same computational logic. This multi-functionality allows the same hardware structure to generate diverse digital values for different ramps, improving productivity without proportionally increasing device complexity.
3Ease of operation
If the electronic circuit modifies the succession of ramps in a simple manner, then the ease of operation is improved, but the adaptability of the digital signal deteriorates
Solution Approach 1:
The patent implements dynamic ramp parameter storage in memory, where the start value, slope, and remaining duration can be programmatically adjusted for each ramp. This dynamic configuration allows users to easily modify the succession of ramps by updating stored parameters, while simultaneously maintaining high adaptability to generate various digital signal patterns including linear ramps, polynomial curves, and complex waveforms.
Solution Approach 2:
The patent enables flexible digital signal generation by allowing independent modification of ramp parameters (start value, slope, duration) stored in memory. By changing these parameters, the circuit can adapt to different application requirements while maintaining simple operation through uniform parameter-based control, resolving the contradiction between ease of operation and signal adaptability.
Data Source
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AI summary
The present description relates to an electronic circuit (10) for supplying a digital signal (Sn) comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of digital values of the digital signal at each cycle of the clock signal, Nout being strictly greater than 1. The electronic circuit includes a first memory (30) in which first data are stored for each ramp, and a second memory (32) in which second data relating to the number of cycles of the clock signal over which some of the ramps extend are stored, and a first circuit (40) configured to read in the first memory the first data relating to several successive ramps and in the second memory the second data associated with said several successive ramps, and to supply said digital values.