Digital Reset Detector Circuit Against Reset Deprivation Attacks
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Solution Overview
Problem
Integrated circuits are vulnerable to hacking through reset deprivation attacks, where attackers exploit unpredictable random states during power-up, rendering existing power-on-reset solutions susceptible to manipulation.
Innovation Solution
A digital reset detector circuit (DRDC) is introduced, comprising a parallel array of memory elements and combinational logic that compares output values to a fixed value to determine if a secure reset has occurred after power-up, providing a secure reset status to protect against reset deprivation attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog POR circuits are used to generate reset pulse duration, then reset protection is provided, but the circuit becomes susceptible to slew-rate attacks that can manipulate reset pulse timing
Solution Approach 1:
The patent replaces analog POR circuits with a digital reset detector circuit that uses digital logic elements (flip-flops, counters, and logic gates) to detect and validate reset signals. This substitution eliminates the vulnerability to analog slew-rate attacks by operating in the digital domain where such continuous signal manipulation is ineffective.
Solution Approach 2:
The invention changes the operating domain from analog to digital, fundamentally altering the parameter space in which reset detection occurs. By using digital signal levels and discrete logic states instead of continuous analog voltages, the system becomes immune to analog manipulation techniques while maintaining reset protection functionality.
2Reliability
If sequential elements with well-defined power-up values are used to generate POR pulse, then reset timing is controlled, but the circuit remains vulnerable to reset deprivation attacks
Solution Approach 1:
The digital reset detector circuit incorporates feedback mechanisms where the detected reset signal is fed back through digital logic to validate the reset condition. The circuit monitors the reset signal, processes it through digital logic elements, and generates a validated reset indication that confirms proper reset occurrence, thereby preventing reset deprivation attacks.
Solution Approach 2:
The patent implements preliminary detection and validation of the reset signal before allowing system operation. The digital reset detector circuit actively monitors and validates the reset condition in advance, ensuring that reset deprivation attacks cannot succeed by withholding or manipulating the reset signal during critical initialization phases.
3Speed
If low voltage threshold is used for reset de-assertion, then reset responds quickly to power-up, but reset may de-assert before logic is fully powered up causing security issues
Solution Approach 1:
The digital reset detector circuit performs preliminary detection and validation of both the reset signal and the powered-up state before allowing operation. By using digital logic to monitor and validate conditions in advance, the system ensures that reset de-assertion only occurs when both the reset signal is proper and the logic is fully powered up, preventing premature operation.
Solution Approach 2:
The invention replaces analog voltage threshold comparison with digital logic-based state detection. Instead of relying on continuous voltage levels that may trigger prematurely, the digital circuit uses discrete logic states and validated signals to determine when reset de-assertion is appropriate, ensuring both speed and reliability.
4Reliability
If high voltage threshold is used for reset de-assertion, then secure state is ensured, but erroneous resets occur during dynamic voltage and frequency scaling
Solution Approach 1:
The digital reset detector circuit dynamically adapts to different operating conditions including DVFS operations. By using digital logic that can distinguish between legitimate reset signals and voltage transitions during scaling, the system maintains secure state initialization while allowing normal DVFS operations without triggering erroneous resets.
Solution Approach 2:
The patent replaces analog voltage threshold triggering with digital logic-based reset detection that can differentiate between various voltage transition patterns. This substitution allows the system to maintain high reliability for secure state initialization while being insensitive to normal voltage fluctuations during DVFS operations.
Data Source
AI summary
Computing devices are now used for various purposes ranging from monitoring a refrigerator to driving automobiles. Protecting the data and logic within the chips of the computing devices is essential to ensure reliable operation. When a particular partition of a chip is powered-up but the logic of the partition is not reset, the logic will be in an unpredictable random state. To operate in a secure environment, it is necessary to start the operation of the logic from a known state and not a random state. To ensure the logic is operating in a secure environment, a digital reset detector circuit (DRDC) is provided that indicates if the logic was reset after power-up. The DRDC can ensure chips are secure from attacks involving reset deprivation upon power-up and help protect various secure and secret assets in a chip, including customer keys.