Digital Power-On Reset Circuit With Self-Disabling Counters
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Solution Overview
Problem
Traditional power on reset circuits in devices consume a constant power, are not finely controllable, and are difficult to port across different devices due to varying power availability and ramp characteristics, leading to undesirable side effects when components are allowed to operate prematurely.
Innovation Solution
A digital power on reset circuit using counters to generate a power on reset signal based on a clock signal, ensuring that components are held in a reset state for a minimum time before being enabled, and then disabling itself to prevent continuous power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional analog power on reset circuits are used, then components are held in reset until power is stable, but the circuits consume constant power even after performing their role
Solution Approach 1:
The digital power on reset circuit operates periodically: it activates when power is applied, holds components in reset for a predetermined time period, asserts the reset signal, and then disables itself. This periodic operation ensures reliable power stabilization while eliminating continuous power consumption after the reset function is completed.
Solution Approach 2:
The digital power on reset circuit is configured to automatically disable itself after asserting the reset signal. This self-service mechanism eliminates the need for external control and ensures that the circuit stops consuming power once its function is fulfilled, while still providing reliable power stabilization during the predetermined time period.
2Reliability
If traditional power on reset circuits are used, then components are protected during power ramp, but the circuits are difficult to port across different devices with varying power characteristics
Solution Approach 1:
The digital power on reset circuit uses a predetermined time period parameter that can be adjusted to match different device power ramp characteristics. By changing this time parameter rather than the circuit architecture itself, the same digital circuit design can be adapted to various devices with different power availability and ramp rates, ensuring component protection while maintaining device portability.
3Productivity
If components are allowed to operate immediately upon power application, then device startup is faster, but components may operate prematurely before power reaches desired level
Solution Approach 1:
The digital power on reset circuit performs preliminary action by automatically disabling the digital electronic component during a predetermined time period after power application. This preliminary protection action prevents premature component operation while keeping the system ready to start quickly once the time period expires and power is confirmed stable.
Data Source
AI summary
Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus includes a digital electronic component configured to produce a clock signal. A first counter is configured to output a first count signal based on the clock signal and a second counter is configured to output a second count signal based on the clock signal. A power on reset logic is configured to provide a power on reset signal based on the first count signal and the second count signal, where the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power.