Digital RF Power Amplifier Duty Cycle Control for Higher Efficiency
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Solution Overview
Problem
Conventional digital RF power amplifiers are inefficient and cannot be effectively controlled using conventional biasing and harmonic matching techniques, posing challenges for integration in small chip designs, especially at wireless telecommunication frequencies between 900 MHz and 5.8 GHz.
Innovation Solution
The implementation of a duty cycle controller that adjusts the duty cycle of a digital signal at the carrier radio frequency before amplification, using a delay unit and logic gate to generate a modified digital signal with an optimized duty cycle, thereby improving the efficiency of the digital power amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional digital RF power amplifiers are used, then the device can be integrated on a digital chip without bulky harmonic tuning networks, but the amplifier efficiency is poor and cannot be controlled with conventional techniques
Solution Approach 1:
The patent changes the duty cycle parameter of the digital RF signal to optimize amplifier efficiency. By adjusting the duty cycle (the ratio of high state duration to total period), the invention enables control over power consumption and efficiency without requiring analog matching networks or harmonic tuning components, thus maintaining integration capability while improving energy efficiency
Solution Approach 2:
The invention introduces dynamic duty cycle adjustment that can be modified in real-time to optimize efficiency under different operating conditions. This dynamic parameter control allows the amplifier to adapt its efficiency characteristics without changing the physical structure or adding bulky external components
2Loss of energy
If the duty cycle is reduced to improve amplifier efficiency, then power loss is reduced, but the signal power and output power may be affected
Solution Approach 1:
The patent systematically adjusts the duty cycle parameter to find the optimal balance point where power loss is minimized while maintaining adequate signal power. By varying the duty cycle and measuring both power loss and output power, the invention identifies the optimal duty cycle value that resolves this contradiction for specific operating conditions
Data Source
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AI summary
An amplification unit reduces a duty cycle of a digital signal at a carrier radio frequency to optimize the efficiency of the RF power amplifier that amplifies the reduced duty cycle signal. An exemplary amplification unit includes a duty cycle controller and a digital power amplifier. A delay unit in the duty cycle controller applies a delay to an input digital signal at the carrier radio frequency to generate a delayed signal at the carrier radio frequency. A logic gate in the duty cycle controller logically combines the input digital signal with the delayed signal to generate a modified digital signal at the carrier radio frequency, where the modified input digital signal has a reduced duty cycle relative to that of the input digital signal. Amplifying the modified digital signal in the digital RF power amplifier generates an amplified analog signal at the carrier radio frequency while improving amplifier efficiency.