Digital Ring PLL Frequency Tuning for Wide Range and Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing PLL circuits face limitations in high frequency applications due to large chip area requirements, sensitivity to power noise, and decreased performance, particularly in digital PLL designs that struggle with high DCO frequency range, long-term jitter control, low power consumption, and quick lock times.
Innovation Solution
A digital phase locked loop control system utilizing a digital controlled ring oscillator with NAND gates, adjustable delay cells, and cycle control mechanisms to precisely tune the oscillator output frequency, eliminating the need for capacitors and reducing chip area while enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional analog PLL circuits are used, then stable frequency generation is achieved, but chip area is significantly large due to multiple capacitors
Solution Approach 1:
The patent replaces the mechanical/analog components (capacitors, resistors, operational amplifiers) with digital logic components. The analog charge pump and low-pass filter are substituted with digital control logic and delay elements, eliminating the need for large capacitors while maintaining PLL functionality through digital signal processing and timing control.
Solution Approach 2:
The patent changes the operating parameters from continuous analog voltage control to discrete digital timing control. The VCO is replaced with a digitally controlled oscillator that adjusts frequency by changing the number of delay elements in the feedback path, transforming the control mechanism from voltage-based to time-based digital control.
2Reliability
If traditional analog PLL circuits are used, then frequency stability is maintained, but sensitivity to power noise is high
Solution Approach 1:
The patent substitutes noise-sensitive analog components with noise-immune digital logic circuits. The analog charge pump and filter stages that are highly sensitive to power supply variations are replaced with digital counters, logic gates, and delay elements that operate with digital voltage levels, significantly reducing sensitivity to power noise while maintaining frequency stability.
3Area of stationary object
If first generation digital PLL is used, then chip area is reduced, but performance is markedly decreased
Solution Approach 1:
The patent introduces dynamic adjustment capabilities to the digital PLL by making the delay path configurable and adjustable. The number of delay elements in the feedback path can be dynamically changed to accommodate different frequency requirements, and the phase detector can be reconfigured for different operating modes, providing adaptability that was missing in first-generation digital PLL designs.
Solution Approach 2:
The patent segments the delay path into multiple configurable delay elements that can be independently controlled. This segmentation allows for fine-grained frequency adjustment and phase control, enabling the digital PLL to achieve high performance with reduced chip area by using only the necessary number of delay elements for the specific application.
4Adaptability or versatility
If digital controlled oscillator with many delay cells is used, then frequency range is expanded, but lock time increases
Solution Approach 1:
The patent segments the frequency adjustment process into coarse and fine tuning stages. The delay path is divided into groups that can be adjusted in steps, allowing the oscillator to quickly acquire the approximate frequency range first, then gradually refine the frequency with smaller adjustments, significantly reducing the overall lock time while maintaining a wide frequency range.
Solution Approach 2:
The patent implements a periodic adjustment strategy where the delay elements are adjusted in discrete steps rather than continuously. The phase detector generates periodic correction signals that adjust the delay path in controlled increments, enabling the system to traverse the frequency range efficiently with a predictable and reduced lock time.
Data Source
AI summary
A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter.