All-Digital SerDes Clock Recovery for CMOS-Compatible Links

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Solution Overview

Problem

Conventional serializer-de-serializer (SerDes) circuitry in integrated circuits relies on analog components that are incompatible with newer CMOS technologies, leading to performance inconsistencies and increased costs due to the use of different supply voltages.

Innovation Solution

The development of all-digital serializer-de-serializer (SerDes) circuitry that replaces analog components with digitally controlled oscillators, phase locked loops, and filters, utilizing a clock multiplier unit and clock and data recovery circuits to achieve serialization and deserialization using matched digitally controlled oscillators and a non-linear phase detector.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If analog components are used in conventional SerDes circuitry, then serialization and deserialization functions are achieved, but compatibility with newer CMOS technologies deteriorates and performance consistency worsens

Engineering Contradiction:

Improvecompatibility with CMOS technologiesVSAvoidperformance consistency

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent replaces analog components (voltage-controlled oscillators, analog phase-locked loops, analog filters) with digital components (digitally controlled oscillators, digital phase-locked loops, digital filters). This substitution of analog systems with digital systems resolves the contradiction by achieving both CMOS compatibility and performance consistency, as digital circuits are inherently more compatible with modern CMOS technology while providing better performance stability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operating parameters and control methods from analog continuous signals to digital discrete signals. By using digitally controlled oscillators with programmable frequency division and digital phase detection, the system achieves better adaptability to CMOS technology while maintaining consistent performance through precise digital control of timing and frequency parameters.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If analog components are used in SerDes circuitry, then serialization and deserialization are achieved, but manufacturing costs increase due to different supply voltages

Engineering Contradiction:

Improvemanufacturing costVSAvoidsupply voltage compatibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal digital architecture where digitally controlled oscillators and digital logic circuits can operate from a single supply voltage, eliminating the need for multiple voltage domains. This universal digital design approach reduces manufacturing complexity and cost while maintaining full functionality of the SerDes system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

By replacing analog components that require specific voltage levels with digital components that can operate from standard CMOS supply voltages, the patent eliminates the need for voltage conversion circuits and multiple power domains, thereby reducing manufacturing cost and improving ease of production.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Ease of manufacture

If all-digital components are used in SerDes circuitry, then compatibility with CMOS technologies and cost-effectiveness are improved, but circuit complexity increases

Engineering Contradiction:

Improvecost-effectivenessVSAvoidcircuit complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges multiple digital functions into integrated blocks: the digitally controlled oscillator incorporates frequency division capability, the digital phase-locked loop integrates phase detection and timing recovery, and the digital filter combines signal conditioning and equalization. This functional integration reduces the overall number of separate components and simplifies the circuit architecture despite the advanced digital functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The all-digital components are designed with multi-functionality: the digitally controlled oscillator serves both as a clock source and frequency divider, the digital phase-locked loop performs both phase synchronization and timing recovery, and the digital filter handles both signal equalization and noise filtering. This multi-functionality reduces the total component count and simplifies the overall circuit design.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7656323B2Apparatus for all-digital serializer-de-serializer and associated methods

Publication Date: 2010.02.02 ALTERA CORP

AI summary

An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.