Digital Signal Line Signaling to Reduce Capacitive Coupling
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Solution Overview
Problem
Existing digital signaling techniques, such as return-to-zero signaling, still experience capacitive coupling between digital signal lines due to current flow, even when multiple high logic levels are being output, which reduces performance.
Innovation Solution
Dynamically blocking return-to-zero signaling when both the current and next data outputs are at high logic levels, preventing the return-to-zero voltage level transitions and maintaining the high logic level until the next data output is at a low logic level, thereby reducing current flow and capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If return-to-zero signaling is used to reduce capacitive coupling, then capacitive coupling between signal lines is reduced, but current flow still occurs when multiple high logic levels are output
Solution Approach 1:
The patent implements dynamic control of the return-to-zero signaling by detecting whether the next data output will be at a high logic level. When both current and next data outputs are high, the system dynamically blocks the return-to-zero transition, allowing the signal to remain high throughout the clock cycle. This dynamic adaptation eliminates unnecessary current flow while maintaining capacitive coupling reduction benefits.
Solution Approach 2:
The patent changes the signaling parameter from fixed return-to-zero to conditional return-to-zero. By monitoring the next data output state and adjusting the current output waveform accordingly, the system transforms the signaling approach to eliminate redundant voltage transitions, thereby reducing current flow without compromising signal integrity or increasing capacitive coupling.
2Use of energy by moving object
If return-to-zero signaling transitions are prevented, then current flow is reduced, but signal line voltage levels must be maintained
Solution Approach 1:
The patent introduces a control mechanism that acts as an intermediary between the data output and the signal line. This control logic monitors the next data output state and selectively enables or disables the return-to-zero transition, mediating between the need to reduce current flow and the requirement to maintain proper voltage level stability for reliable digital signaling.
Data Source
AI summary
Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.