Digital Signal Sample Skipping for Microphone Array Delay

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Solution Overview

Problem

Existing solutions for implementing delays in microphone arrays, such as delay lines, are area-consuming and inflexible, particularly when fine tuning is required, leading to unnecessary hardware complexity and energy consumption.

Innovation Solution

A method that applies delays by skipping samples in digital streams before conversion, using decimation filters and a control unit to determine and apply delays, eliminating the need for conventional delay lines and allowing for flexible delay values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional delay lines are used to implement delays in microphone arrays, then the delay precision and flexibility are improved, but the hardware area and device complexity increase significantly

Engineering Contradiction:
Improvedelay precisionVSAvoidhardware area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent replaces the mechanical delay line system with a digital signal processing approach. Instead of using physical delay cells that occupy silicon area, the invention uses sample skipping in the digital domain combined with decimation filtering to achieve the same delay function with minimal hardware overhead.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the approach from fixed hardware delay depths to dynamic sample skipping counts. By varying the number of skipped samples based on the required delay, the system achieves flexible delay values without requiring multiple fixed delay lines, thereby reducing hardware area while maintaining precision.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If delay lines with fine tuning capability are implemented, then the delay adjustment flexibility is improved, but the number of delay cells and hardware complexity increase

Engineering Contradiction:
Improvedelay adjustment flexibilityVSAvoidhardware complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware delay adjustment mechanisms with simple digital control of sample skipping. The processing unit dynamically determines the number of samples to skip based on beamforming requirements, providing fine-tuning capability without additional hardware complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces dynamic delay adjustment by allowing the number of skipped samples to vary in real-time based on the beamforming algorithm requirements. This dynamic approach replaces static hardware delay lines with flexible digital control, improving adaptability without increasing hardware complexity.

Inventive Principle:
Principle #15Dynamics

3Reliability

If the number of delay cells is designed for the worst case, then the reliability for all cases is improved, but the hardware area is unnecessarily large for most cases

Engineering Contradiction:
Improvedelay coverage reliabilityVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes from fixed worst-case delay depth to dynamic sample skipping based on actual requirements. The processing unit calculates the exact number of samples to skip for each microphone path, ensuring reliable delay coverage for all cases while using minimal hardware area since no large fixed delay lines are needed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10264353B2Method of processing digital signals, in particular digital acoustic signals, by sample skipping and decimation filtering and corresponding device
Publication Date: 2019.04.16 STMICROELECTRONICS INT NV
  • US10264353B2 patent drawing
  • US10264353B2 patent drawing
  • US10264353B2 patent drawing

AI summary

Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.