Digital SSCG Delay Line for EMI Reduction
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Solution Overview
Problem
Existing methods for reducing electromagnetic interference (EMI) in electronic products, such as home theater systems and DVD players, are costly and inefficient, particularly due to the need for increased shielding and the limitations of analog spread spectrum clock generation (SSCG) techniques.
Innovation Solution
A digital spread spectrum clock generator (SSCG) system that modulates the system clock using a digital delay line and logic block, allowing for frequency shifting without modifying the existing clock generator, and includes self-calibration for process and temperature variations, enabling reduced EMI with minimal hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If analog spread spectrum clock generation is used, then EMI reduction is achieved, but product integration time increases and performance predictability decreases
Solution Approach 1:
The patent replaces the analog SSCG system with a fully digital implementation. The digital delay line and logic block process clock signals through digital logic operations rather than analog voltage modulation, enabling faster integration and better predictability while maintaining EMI reduction functionality.
Solution Approach 2:
The patent changes the fundamental operating parameters from analog voltage control to digital logic states. By using digital delay elements and logic blocks, the system achieves precise control of clock signal timing through discrete digital operations, improving integration time and performance consistency.
2Object-affected harmful factors
If frequency is modulated up from reference in digital system, then EMI reduction is achieved, but setup and hold time margin is reduced
Solution Approach 1:
The patent implements dynamic frequency modulation through a digital delay line that can be programmably adjusted. The delay line responds to control signals to dynamically change the effective delay, enabling frequency modulation that adapts to system conditions while maintaining reliable timing margins through digital precision.
Solution Approach 2:
The system incorporates feedback mechanisms where the delayed clock signal is fed back to the logic block. This feedback allows the system to monitor and adjust timing parameters in real-time, ensuring that frequency modulation for EMI reduction does not compromise setup and hold time requirements.
3Object-affected harmful factors
If frequency is modulated down from reference in digital system, then EMI reduction is achieved, but system speed capability is reduced
Solution Approach 1:
The digital delay line provides dynamic adjustment capability, allowing the system to modulate frequency downward for EMI reduction when needed, while being able to quickly return to higher frequencies when speed capability is required. The programmable nature of the delay line enables flexible adaptation between these opposing requirements.
4Object-affected harmful factors
If shielding is increased to reduce EMI, then EMI compliance is achieved, but hardware cost and assembly complexity increase
Solution Approach 1:
The patent substitutes mechanical shielding solutions with a digital signal processing approach. By implementing spread spectrum clock generation through digital logic, the system reduces EMI at the source rather than relying on physical shielding barriers, thereby reducing hardware complexity and assembly requirements.
Data Source
AI summary
A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.