Digital Storage Element With Clock Gating For Scan Testing
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Solution Overview
Problem
Integrated circuits face issues with set-up time violations, hold-time violations, and unnecessary power consumption during scan-based testing due to the limitations of existing digital storage elements, particularly in ensuring reliable data sampling and efficient clocking mechanisms.
Innovation Solution
The implementation of a digital storage element architecture that includes a master transparent latch and a slave transparent latch, with a clock gating element that gates off the clock to the slave latch based on an enable signal, using dual, non-overlapping scan clocks to avoid hold timing violations and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used to operate both master and slave latches, then the circuit complexity is reduced, but hold time violations occur and reliability deteriorates
Solution Approach 1:
The clock signal is segmented into two separate non-overlapping scan clocks (SCK1 and SCK2) that operate the master and slave latches at different times. This segmentation prevents hold time violations by ensuring the master latch captures data before the slave latch updates, while maintaining manageable circuit complexity through systematic clock distribution.
2Productivity
If the slave latch operates continuously during scan mode, then data shifting is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The slave latch operates periodically rather than continuously by using the non-overlapping scan clock SCK1 only during required update phases. The clock gating element enables the slave latch to remain inactive during master latch capture phases, reducing unnecessary power consumption while maintaining scan operation continuity when needed.
3Reliability
If external delay buffers are added to prevent hold time violations, then reliability improves, but device complexity and area increase
Solution Approach 1:
The non-overlapping scan clocks SCK1 and SCK2 serve as intermediaries that coordinate the operation of master and slave latches without requiring external delay buffers. These clocks act as mediators that naturally enforce the required timing separation between data capture and update operations, improving reliability while avoiding additional external components.
4Speed
If the master latch updates before the slave latch captures, then speed is improved, but set-up time violations occur
Solution Approach 1:
The master latch performs preliminary data capture action before the slave latch updates, using the non-overlapping clock sequence where SCK2 (master clock) operates first. This preliminary action ensures data is stable and captured correctly before the slave latch uses SCK1 to update, maintaining set-up time compliance while enabling fast sequential operation.
Data Source
AI summary
A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.