Digital Phase-Frequency Synchronizer for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional voltage controllers in electronic devices often occupy large device areas and have complex circuitry, making them unsuitable for devices with limited space and simpler circuitry requirements.
Innovation Solution
The implementation of fully integrated voltage regulators (FIVRs) with a synchronizer component that includes a digital control oscillator and adaptive update-rate control, which reduces device area and complexity by using a phase and frequency detector to adjust the clock signal phase and frequency, thereby controlling the voltage outputs efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If analog implementation is used for voltage controller components, then the device area consumed is relatively large, but the implementation is simpler
Solution Approach 1:
The patent merges the phase detector and frequency detector into a single integrated phase-frequency detector unit. This consolidation reduces the overall device area by eliminating separate detector circuits while maintaining the functionality of both detection operations within a unified digital logic structure.
Solution Approach 2:
The phase-frequency detector is designed to perform multiple functions: it detects both phase differences and frequency differences between clock signals simultaneously. This multi-functional approach replaces what would traditionally require separate analog circuits, thereby reducing device area while keeping the implementation digitally manageable.
2Area of stationary object
If digital implementation is used for voltage controller components, then the device area is reduced, but the circuitry becomes complex
Solution Approach 1:
The charge pump functionality is merged with the phase-frequency detector into an integrated unit. This combination allows the circuit to operate as a unified digital block that handles both detection and charge pumping operations, reducing the need for separate complex digital circuits while maintaining area efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the charge pump is fed back to the phase-frequency detector through a loop filter. This feedback loop enables the system to automatically adjust and maintain synchronization, reducing the need for complex external control circuits and simplifying the overall digital implementation.
3Reliability
If conventional voltage controllers are used, then voltage regulation is achieved, but the lock time is slow and jitter is high
Solution Approach 1:
The phase-locked loop operates with periodic sampling and adjustment cycles. The phase-frequency detector continuously samples the phase and frequency differences at regular intervals, and the charge pump applies periodic correction pulses. This periodic operation enables faster convergence to lock compared to conventional continuous analog adjustment, reducing lock time while maintaining stability.
Solution Approach 2:
The patent replaces conventional analog mechanical-like adjustment mechanisms with digital logic operations. The phase-frequency detector uses digital logic to detect phase and frequency differences, and the charge pump uses digital control to generate correction pulses. This substitution enables faster response times and reduced jitter compared to analog mechanisms, while maintaining regulation stability.
Data Source
AI summary
Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.