Digital Frequency Synthesis With PI Control for Low-Jitter Clocks
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Solution Overview
Problem
Conventional clock management circuits in integrated circuits face challenges in achieving low output jitter and phase alignment simultaneously, especially when dealing with input clock jitter, which can lead to system instability and loss of lock.
Innovation Solution
A digital frequency synthesis implementation that uses a phase detector and a synthesizer control block with integral and proportional adjustment filters, along with a fractional counter and delta sigma circuit, to generate a clock signal that is phase locked without hard phase alignment, reducing output jitter and achieving PLL-like performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog PLL implementation is used to achieve fine timing resolution, then timing precision is improved, but power supply complexity and area increase
Solution Approach 1:
The patent replaces the analog mechanical system with a digital system. Specifically, it substitutes the analog voltage-controlled oscillator and continuous analog feedback loop with a digital delay line and digitally controlled oscillator, maintaining fine timing resolution while eliminating complex power supply requirements and large loop filter elements
Solution Approach 2:
The patent changes the operating parameters from continuous analog values to discrete digital values. The continuous gain from phase error signal is replaced with digitally quantized gain, and the oscillator frequency control transitions from voltage-based to digital code-based control, simplifying power supply requirements while maintaining precision
2Use of energy by moving object
If digital PLL implementation is used to reduce power consumption and improve noise immunity, then power efficiency is improved, but loop filter complexity and area increase
Solution Approach 1:
The patent extracts and removes the complex digital loop filter from the system by implementing a simplified architecture where the phase detector output directly controls the delay line without requiring a large digital filter, significantly reducing area while maintaining low power consumption and noise immunity
Solution Approach 2:
The patent uses a simplified digital architecture that copies the essential functionality of analog PLLs without requiring complex digital loop filters, achieving similar performance with reduced area through direct digital control of the delay line
3Device complexity
If conventional digital PLL with quantized gain is used to simplify circuitry, then device complexity is reduced, but timing precision deteriorates
Solution Approach 1:
The patent implements a dynamic delay line where the delay amount can be continuously adjusted in fine increments using a digital control signal. This dynamic adjustment capability allows the system to achieve fine timing precision while maintaining circuit simplicity through direct digital control without requiring complex loop filters
4Measurement precision
If analog PLL with continuous gain is used to maintain phase alignment, then phase alignment precision is improved, but area and power supply requirements increase
Solution Approach 1:
The patent replaces the continuous analog gain mechanism with a digital delay line controlled by digital signals. The phase alignment precision is maintained through fine-grained digital delay adjustment, eliminating the need for large analog components and complex power supply arrangements
Data Source
AI summary
An integrated circuit for providing digital frequency synthesis is disclosed. For example, the integrated circuit comprises a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein the phase detector outputs an error signal. The integrated circuit further comprises a synthesizer control block, coupled to the phase detector, for receiving the error signal to generate a delay select signal, wherein the synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter.