Digital Synthesizer Loop Bandwidth Switching for Fast FMCW Reset
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Solution Overview
Problem
Modern FMCW radar systems face limitations in reset time due to the inherent constraints of ADPLLs, which are not adequately addressed by existing technologies, resulting in wasted time between successive ramps and suboptimal performance.
Innovation Solution
A digital synthesizer with a modulation generator that produces frequency control words and a gear-shift signal to dynamically select gains, allowing for adjustable loop bandwidth without frequency jumps, enabling faster reset times and increased refresh rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the PLL bandwidth is set wide to reduce reset time, then the reset time is reduced, but the phase noise increases
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by switching between a first bandwidth (narrow) during ramp-up and a second bandwidth (wide) during reset. This allows the system to have narrow bandwidth for low phase noise during signal processing and wide bandwidth for fast reset when returning to start frequency, thereby resolving the contradiction between reset time and phase noise
Solution Approach 2:
The patent changes the PLL bandwidth parameter at different operational stages. During ramp-up, a narrow bandwidth is used to minimize phase noise, while during reset, a wide bandwidth is used to minimize reset time. This parameter switching resolves the contradiction by adapting the bandwidth to the specific operational requirement
2Object-affected harmful factors
If the PLL bandwidth is set narrow to reduce phase noise, then the phase noise is reduced, but the reset time increases
Solution Approach 1:
The system dynamically adjusts bandwidth based on operational phase: narrow during ramp-up for low phase noise, wide during reset for fast reconfiguration. This temporal separation of bandwidth settings resolves the contradiction by ensuring each parameter is optimized for its specific operational context
Solution Approach 2:
The patent employs periodic switching between narrow and wide bandwidth modes corresponding to the periodic operation of ramp-up and reset phases. This periodic parameter adjustment allows the system to achieve both low phase noise during signal processing and fast reset during reconfiguration
3Loss of time
If gear-shifting is used to speed up PLL lock time, then the lock time is reduced, but frequency jumps occur at each gear shift
Solution Approach 1:
The patent applies preliminary frequency adjustment before the actual frequency change to prevent jumps. The TDC measures the frequency difference and applies a compensating offset in advance, ensuring smooth transitions without frequency jumps while still achieving fast reset
4Device complexity
If the ADPLL supports only decreasing loop gains, then the implementation is simpler, but the versatility is limited
Solution Approach 1:
The patent implements a universal gear-shifting mechanism that supports both increasing and decreasing loop gains through the same hardware structure. The offset calculation circuit and TDC work together to handle bidirectional gain changes, providing versatility while maintaining implementation simplicity
Data Source
AI summary
A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; andcalculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.