Digital Synthesizer Gain Compensation for Stable FMCW ADPLL Bandwidth
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Solution Overview
Problem
Modern FMCW radar systems face challenges in maintaining a constant ADPLL bandwidth during wide-frequency modulation ramps due to varying DCO gain, which introduces phase noise and is difficult to achieve with existing ADPLLs, especially in applications like automotive radar where high linearity and low phase noise are critical.
Innovation Solution
A digital synthesizer that generates frequency-dependent gain to compensate for DCO gain variations, maintaining a substantially constant open-loop gain across the DCO operating frequency range by dynamically adjusting the frequency-dependent gain during FMCW radar ramps, using a modulation generator to produce frequency control words and estimated DCO gain values, and applying these gains through a gain circuit to ensure consistent ADPLL bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the ADPLL bandwidth is set narrow to reduce phase noise, then phase noise performance improves, but the linearity of FMCW ramps deteriorates
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by varying the loop filter cutoff frequency during FMCW operation. The bandwidth is widened during frequency sweeping to maintain linearity, then narrowed during hold periods to reduce phase noise, allowing both requirements to be satisfied at different times in the modulation cycle
Solution Approach 2:
The patent changes the loop filter cutoff frequency parameter dynamically based on the modulation phase. By adjusting this parameter in response to the FMCW ramp state, the system optimizes both linearity during sweeps and phase noise during stable periods
2Adaptability or versatility
If the DCO gain varies with frequency during ramp modulation, then the DCO adapts to frequency changes, but the ADPLL bandwidth varies from the optimum value
Solution Approach 1:
The patent employs feedback mechanisms where the measured or estimated DCO gain is used to adjust the loop filter characteristics. This feedback loop compensates for DCO gain variations, maintaining optimal ADPLL bandwidth despite frequency-dependent DCO behavior
Solution Approach 2:
The patent dynamically adjusts the loop filter cutoff frequency parameter in response to DCO gain variations. By changing this parameter based on the operating frequency and DCO characteristics, the system maintains stable ADPLL bandwidth across the frequency range
3Measurement precision
If a long convergence time is acceptable for DCO gain measurement, then measurement accuracy improves, but the system becomes unusable for wide frequency range applications
Solution Approach 1:
The patent performs DCO gain measurements in advance during calibration phases or hold periods, storing the measured values for later use. This preliminary measurement approach allows accurate characterization of DCO gain across the frequency range without impacting real-time operation speed
Solution Approach 2:
The patent implements dynamic bandwidth adjustment by varying the loop filter cutoff frequency during FMCW operation. The bandwidth is widened during frequency sweeping to maintain linearity, then narrowed during hold periods to reduce phase noise, allowing both requirements to be satisfied at different times in the modulation cycle
Data Source
AI summary
A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.