Automatic Learning Digital Test Vector Correction
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Solution Overview
Problem
The existing methods for writing and debugging digital vectors in complex logic chips are labor-intensive and prone to errors, requiring repeated manual modifications and verifications, which significantly reduces development efficiency.
Innovation Solution
An automatic learning method and system for digital test vectors that writes a pattern file with input pin timing and configures the output pin timing in a learning state, allowing for self-correction based on recorded running states to achieve a final pattern file within a set threshold range, utilizing an upper computer, pattern generator, driver, comparator, and history random access memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual writing and debugging of pattern files is performed, then the test coverage can be ensured, but the development efficiency is greatly reduced and the process is labor-intensive
Solution Approach 1:
The system automatically learns and generates output pin timing patterns by observing the device under test during runtime. The pattern file is executed, the actual output states are captured via comparator and HRAM, and the system self-corrects the pattern file without manual intervention, making the debugging process self-service oriented
Solution Approach 2:
The system implements a feedback loop where the actual output pin states are compared against expected patterns, the discrepancies are captured and stored in HRAM, and this feedback information is used to automatically correct the pattern file for subsequent iterations, improving test coverage while reducing manual effort
2Manufacturing precision
If manual modification and verification of pattern files is performed repeatedly, then the timing accuracy can be improved, but the time consumption increases significantly
Solution Approach 1:
The system pre-configures the output pin timing in a learning state (marked by 'E') before execution. During runtime, the actual timing information is captured and stored in HRAM. This preliminary setup eliminates the need for repeated manual timing adjustments, achieving high timing accuracy while minimizing time consumption
Solution Approach 2:
The manual mechanical process of repeatedly editing and verifying pattern files is replaced by an automated electronic system. The comparator captures actual output states, HRAM stores the timing data, and the upper computer automatically generates corrected pattern files, substituting manual mechanical editing with automated electronic processes
3Ease of operation
If the output pin timing is configured in learning state and automatically corrected, then the debugging difficulty is reduced, but the system complexity increases
Solution Approach 1:
The system introduces intermediate components (comparator, HRAM, and upper computer) that mediate between the device under test and the pattern generation. The comparator acts as an intermediary to capture actual output states, HRAM serves as an intermediary storage for timing data, and the upper computer acts as an intermediary to process and generate corrected patterns, reducing debugging difficulty despite increased system complexity
Data Source
AI summary
The present disclosure discloses an automatic learning method and system for a digital test vector. The system includes an upper computer, a pattern generator PG, a driver DRIVER, a comparator COMPARE and a history random access memory HRAM. The method includes: writing a pattern file, the pattern file including an input pin timing and an output pin timing, wherein the input pin timing is provided by a device under test, and the output pin timing is configured to be in a learning state; running the pattern file, and recording a running state; reading recorded running state data, and acquiring an output pin state, recorded within certain time, in the running state data; and correcting the output pin timing in the running pattern file according to the acquired output pin state to obtain a corrected output timing, thus obtaining a corrected pattern file. The present disclosure greatly improves the development efficiency, reduces writing of the characteristic of an output pin of a chip, and lowers the writing difficulty.