Digital-to-Time Converter with Fractional Delay Jitter Control
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Solution Overview
Problem
Conventional digital-to-time converters in clock synthesizers face challenges in achieving high frequency resolution while maintaining low phase noise, leading to increased power consumption and limited bandwidth, which fails to meet performance specifications as frequencies increase.
Innovation Solution
A digital-to-time converter is designed with a phase interpolator and dynamic feedback divider, using a time-domain digital-to-analog converter to reduce control voltage ripple and jitter, incorporating a fixed slew rate delay cell and capacitor-based units for linear delay control, and employing background calibration to correct gain errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional divider is used to achieve high frequency resolution, then frequency resolution is improved, but deterministic jitter increases and dominates the jitter performance
Solution Approach 1:
The feedback divider is segmented into two independent parts: an integer divider (divide-by-N) and a fractional delay element (divide-by-P). This segmentation allows the system to achieve fractional frequency division (N + P/M) while keeping the integer divider deterministic and the fractional part isolated to a controlled delay element, thereby maintaining low jitter performance while achieving high frequency resolution.
2Speed
If the loop bandwidth is increased to support higher data rates, then bandwidth is improved, but phase noise from the VCO increases
Solution Approach 1:
The patent implements a feedback mechanism where the fractional delay element receives feedback from the phase detector output. This feedback allows the system to dynamically adjust the fractional delay to compensate for phase errors, enabling higher loop bandwidths to be used without excessive phase noise accumulation, as the feedback continuously corrects the VCO phase deviations.
3Speed
If conventional digital-to-time converters are used at higher frequencies, then frequency coverage is improved, but performance specifications are not met due to increased jitter
Solution Approach 1:
The patent introduces a fractional delay element as an intermediary component between the integer divider and the phase detector. This intermediary element specifically addresses the timing errors introduced at higher frequencies by providing fine-grained fractional delay adjustment, thereby maintaining performance specifications even at elevated frequency operations where conventional converters fail.
Data Source
AI summary
A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.