Digital Timing Recovery with Low-Complexity Equalizer Stability
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Solution Overview
Problem
Existing digital communications receivers face challenges in timing recovery due to interactions between linear adaptive equalizers and timing recovery apparatus, leading to excessive time delays and compromised performance, especially when operating with FIR filters and finite coefficient adjustments.
Innovation Solution
A method for stabilizing the timing interaction between a timing recovery entity and a linear adaptive equalizer by carefully choosing the form of the equalizer coefficients, allowing simultaneous adaptation and maintaining stable timing characteristics, which is implemented using a low-complexity digital linear equalizer that automatically adjusts parameters to compensate for low-pass impairments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a linear adaptive equalizer is operated simultaneously in series with a timing recovery apparatus, then the channel response can be compensated, but the group delay characteristic of the equalizer interacts with the timing adjustment, leading to excessive time delays and compromised performance
Solution Approach 1:
The patent extracts the timing adjustment function from the equalizer output and applies it at the ADC input instead. By recovering timing from the raw ADC samples before equalization and feeding it back to adjust the ADC sampling instances, the system avoids the interaction between equalizer group delay and timing adjustment, thereby eliminating excessive time delays while preserving channel compensation capabilities
Solution Approach 2:
The patent introduces an intermediary timing recovery apparatus that operates on the raw ADC output signals before they enter the equalizer. This intermediary component recovers timing information and adjusts ADC sampling instances, serving as a mediator that prevents the harmful interaction between equalizer group delay and timing adjustment from occurring in the first place
2Speed
If the timing adjustment process operates faster than the group delay characteristic updates, then timing can be adjusted more responsively, but the interaction between equalizer and timing recovery apparatus becomes more difficult to control
Solution Approach 1:
The patent inverts the conventional approach by having the timing recovery apparatus operate on raw ADC samples before equalization rather than on equalizer output. This inversion eliminates the need for coordination between equalizer and timing recovery processes, as they operate in reverse sequence with the timing adjustment occurring first at the ADC input, thereby reducing device complexity while maintaining high timing adjustment speed
3Stability of the object's composition
If equalizer coefficients are constrained to fix the group delay characteristic, then timing stability can be improved, but the equalizer's ability to compensate channel response is reduced
Solution Approach 1:
The patent extracts the timing stability function from the equalizer by implementing timing recovery on raw ADC samples before equalization. This separation allows the equalizer to operate with unconstrained coefficients, maintaining full adaptability for channel compensation, while timing stability is achieved independently through the timing recovery apparatus that adjusts ADC sampling instances based on recovered timing information
Data Source
AI summary
A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique for automatically adjusting the parameters of a digital linear equalizer to compensate for low-pass impairments while maintaining a relatively constant timing characteristic is described.