Digital Timing Pickoff for PET Imaging Jitter Reduction
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Solution Overview
Problem
Conventional PET imaging systems face inaccuracies in determining photon detection times due to the introduction of uncertainty and jitter from analog delay elements in discriminators, leading to mis-identified coincidences and reduced event localization accuracy.
Innovation Solution
The implementation of a timing pickoff system that uses digital components, such as FPGAs or custom ASICs, to determine pulse trigger times without an analog delay element, reducing jitter and improving timing accuracy by generating logic signals based on programmable voltage thresholds and digital processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog delay element is used in a leading edge discriminator to ensure proper timing of logic signals, then the discriminator can correctly identify valid pulses, but jitter is introduced due to electronics noise and component variations, degrading trigger time accuracy
Solution Approach 1:
The patent replaces the analog delay element (electronic/mechanical system) with a digital timing pickoff system using FPGAs or ASICs. The digital system captures the trigger time at the moment the signal crosses the threshold voltage without requiring analog delay circuits, thereby eliminating the jitter introduced by electronics noise and component variations while maintaining proper pulse validation.
Solution Approach 2:
The timing pickoff system performs preliminary action by capturing the trigger time instantaneously when the signal crosses the threshold voltage, before any analog delay processing occurs. This preliminary timing capture ensures accurate time measurement is established prior to subsequent digital signal processing, avoiding the jitter problem of analog delay elements.
2Productivity
If conventional analog discriminators are used to determine trigger times, then the system can identify coincidences, but the jitter from analog components reduces coincidence time resolution and event localization accuracy
Solution Approach 1:
The patent substitutes the entire analog discriminator system with a digital timing pickoff system implemented in FPGAs or ASICs. This digital implementation eliminates analog component jitter while preserving the coincidence identification capability, thereby improving coincidence time resolution and event localization accuracy without sacrificing productivity.
3Ease of operation
If an analog delay element is included in the discriminator circuit, then the system can gate logic signals properly, but process voltage and temperature variations cause jitter that affects output signal timing
Solution Approach 1:
The patent replaces the analog delay element with a digital timing pickoff system that uses digital logic to gate signals. The FPGA or ASIC implementation provides stable digital gating functionality without the sensitivity to process voltage and temperature variations that plagues analog circuits, thereby maintaining ease of operation while improving output signal timing accuracy.
Data Source
AI summary
Systems and methods include an analog-to-logic circuit and a digital processing component. The analog-to-logic circuit receives a first electrical signal, outputs a first logic signal indicating whether or not a voltage of the first pulse is greater than a first threshold voltage, and outputs a second logic signal indicating whether or not the voltage of the first pulse is greater than a second threshold voltage. The digital processing component receives the first logic pulse and the second logic pulse, determines, based on the second logic signal, if the first pulse is valid, and determines, based on the first logic signal, a first trigger time associated with the first pulse.