Digital Up-Conversion Using Non-Overlapping Clock Sampling
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Solution Overview
Problem
Conventional digital polar transmitters for wireless communication systems require high clock rates, consuming large area and power, and degrade Error Vector Magnitude (EVM) with increasing signal bandwidth, while I/Q RF DACs are area-intensive and power-inefficient, posing a challenge for low-cost, low-power, and high-bandwidth digital signal transmission.
Innovation Solution
A digital signal up-converting apparatus comprising a clock generating circuit, an adjusting circuit, and a sampling circuit that generates non-overlapping clock signals to sample and combine digital output signals, reducing power consumption and area while maintaining signal integrity by using a switch amplifier to prevent simultaneous differential device activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a digital polar transmitter is used to transmit RF signal, then area efficiency and power efficiency are improved, but large area and digital power are consumed due to high clock rate CORDIC
Solution Approach 1:
The patent segments the up-conversion process into multiple stages using different clock rates. A first CORDIC unit operates at a first clock rate to perform initial up-conversion, while a second CORDIC unit operates at a second clock rate to perform final up-conversion. This segmentation allows each unit to operate at optimized clock rates, reducing the overall area and power consumption compared to a single high-clock-rate CORDIC unit.
Solution Approach 2:
The patent transitions from a single high-clock-rate digital processing dimension to a multi-dimensional approach using multiple clock rates and parallel CORDIC units. By operating CORDIC units at different clock rates and combining their outputs, the system achieves the same functionality with reduced area and power requirements.
2Adaptability or versatility
If the signal bandwidth increases in digital polar transmitter, then bandwidth is improved, but EVM degrades due to truncation mechanism
Solution Approach 1:
The patent segments the bandwidth handling into multiple CORDIC units operating at different clock rates. Each unit processes a portion of the signal spectrum, allowing the system to accommodate wider bandwidths without requiring a single high-clock-rate unit that would necessitate aggressive truncation. This segmented approach maintains signal integrity and EVM performance across wider bandwidths.
3Reliability
If I/Q RF DAC is used to convert baseband data IQ in RF signal, then signal integrity is maintained, but double silicon area is required to deliver the same amount of power
Solution Approach 1:
The patent replaces the conventional I/Q RF DAC architecture with a digital up-conversion architecture using multiple CORDIC units. Instead of using a high-speed DAC that requires significant area to maintain signal integrity, the system uses digital signal processing at multiple clock rates to achieve the same result with reduced area while maintaining signal integrity.
Data Source
AI summary
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.